fix Sum, Sub, Div, Mul and Sqrt models

ra3xdh · Jan 2, 2024 · 391d7b6 · 391d7b6
1 parent 241df98
commit 391d7b6
Showing 1 changed file with 47 additions and 1 deletion.
diff --git a/library/Ideal.lib b/library/Ideal.lib
@@ -10,6 +10,12 @@ VCVS:SRC1 _net0 _net1 _net2 gnd G="1" T="0"
 VCVS:SRC2 _net3 _net2 gnd gnd G="1" T="0"
 .Def:End
   </Model>
+  <Spice>
+.SUBCKT Ideal_VSum 0 _net0 _net3 _net1 
+ESRC1 _net1 _net2 _net0 0 1
+ESRC2 _net2 0 _net3 0 1
+.ENDS
+  </Spice>
   <Symbol>
     <.ID 10 14 VADD>
     <.PortSym 0 -30 1 0>
@@ -36,6 +42,12 @@ VCVS:SRC1 _net0 _net1 _net2 gnd G="1" T="0"
 VCVS:SRC2 _net3 _net2 gnd gnd G="-1" T="0"
 .Def:End
   </Model>
+  <Spice>
+.SUBCKT Ideal_VSub 0 _net0 _net3 _net1 
+ESRC1 _net1 _net2 _net0 0 1
+ESRC2 _net2 0 _net3 0 -1
+.ENDS
+  </Spice>
   <Symbol>
     <.ID 10 14 VSUB>
     <.PortSym 0 -30 1 0>
@@ -67,6 +79,15 @@ EDD:D1 _net0 gnd _net1 gnd gnd _net2 I1="D1.I1" Q1="D1.Q1" I2="D1.I2" Q2="D1.Q2"
   Eqn:EqnD1Q3 D1.Q3="0" Export="no"
 .Def:End
   </Model>
+  <Spice>
+.SUBCKT Ideal_Mul 0 _net0 _net1 _net2
+HSRC1 _net2 0  VSRC1 1
+VSRC1 0 _net3 DC 0 
+BD1I0 _net0 0 I=0
+BD1I1 _net1 0 I=0
+BD1I2 _net3 0 I=V(_net0)*V(_net1)
+.ENDS
+  </Spice>
   <Symbol>
     <.ID 10 14 MUL>
     <.PortSym 0 -30 1 0>
@@ -97,6 +118,15 @@ EDD:D1 _net0 gnd _net1 gnd gnd _net2 I1="D1.I1" Q1="D1.Q1" I2="D1.I2" Q2="D1.Q2"
   Eqn:EqnD1Q3 D1.Q3="0" Export="no"
 .Def:End
   </Model>
+  <Spice>
+.SUBCKT Ideal_Div 0 _net0 _net1 _net2 
+BD1I0 _net0 0 I=0
+BD1I1 _net1 0 I=0
+BD1I2 _net3 0 I=V(_net0)/(V(_net1)+1E-160)
+HSRC1 _net2 0  VSRC1 1
+VSRC1 0 _net3 DC 0 
+.ENDS
+  </Spice>
   <Symbol>
     <.ID 10 14 DIV>
     <.PortSym 0 -30 1 0>
@@ -126,6 +156,14 @@ EDD:D1 _net2 gnd gnd _net0 I1="D1.I1" Q1="D1.Q1" I2="D1.I2" Q2="D1.Q2"
   Eqn:EqnD1Q2 D1.Q2="0" Export="no"
 .Def:End
   </Model>
+  <Spice>
+.SUBCKT Ideal_Sqrt 0 _net0 _net1 
+HSRC1 _net1 0  VSRC1 1
+VSRC1 0 _net2 DC 0 
+BD1I0 _net0 0 I=0
+BD1I1 _net2 0 I=(V(_net0)<=0)?0:sqrt(V(_net0)+1E-323)
+.ENDS
+  </Spice>
   <Symbol>
     <.ID -20 24 SQRT>
     <.PortSym -30 0 1 0>
@@ -441,6 +479,14 @@ EDD:D1 _net2 gnd gnd _net0 I1="D1.I1" Q1="D1.Q1" I2="D1.I2" Q2="D1.Q2"
   Eqn:EqnD1Q2 D1.Q2="0" Export="no"
 .Def:End
   </Model>
+  <Spice>
+.SUBCKT Ideal_HardLimiter 0 _net2 _net1 VLIMP=14 VLIMN=-14 
+HSRC1 _net1 0  VSRC1 1
+VSRC1 _net0 0 DC 0 
+B2 0 _net0  I = (V(_net2)<0)?VLIMN:VLIMP 
+B1 _net2  0  I = 0
+.ENDS
+  </Spice>
   <Symbol>
     <.ID -20 33 LIM "0=VLIMP=14=Positive voltage limit (V)" "0=VLIMN=-14=Negative voltage limit (V)">
     <.PortSym -30 0 1 0>
@@ -811,4 +857,4 @@ ESRC1 _net05 0 _net04 0 2
     <.PortSym 30 0 2 180>
     <.PortSym -30 0 1 0>
   </Symbol>
-</Component>
+</Component>