From 6cfd1b29ff0c0ef5bf3e2122c3b5ebe2654dd753 Mon Sep 17 00:00:00 2001
From: Rouven Spreckels <rs@qu1x.dev>
Date: Sat, 13 May 2023 09:39:32 +0200
Subject: [PATCH] Remove unsupported trait bounds.

---
 RELEASES.md          | 3 ++-
 src/real/mod.rs      | 4 ++--
 src/simd_bits/mod.rs | 4 ++--
 src/simd_real/mod.rs | 4 ++--
 4 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/RELEASES.md b/RELEASES.md
index 2cba92f..68bf445 100644
--- a/RELEASES.md
+++ b/RELEASES.md
@@ -1,5 +1,6 @@
-# Version 0.7.4 (2023-05-03)
+# Version 0.7.4 (2023-05-13)
 
+  * Fix build by removing `Octal`/`LowerExp + UpperExp + Display` bound.
   * Fix build by using explicit `FromStr<Err = ParseFloatError>` bound.
   * Update KaTeX.
 
diff --git a/src/real/mod.rs b/src/real/mod.rs
index fea1808..3be6f11 100644
--- a/src/real/mod.rs
+++ b/src/real/mod.rs
@@ -10,7 +10,7 @@ use super::{ApproxEq, Bits, SimdReal};
 use core::{
 	cmp::Ordering,
 	convert::FloatToInt,
-	fmt::{Debug, Display, LowerExp, UpperExp},
+	fmt::Debug,
 	iter::{Product, Sum},
 	num::{FpCategory, ParseFloatError},
 	ops::{Add, AddAssign, Div, DivAssign, Mul, MulAssign, Neg, Rem, RemAssign, Sub, SubAssign},
@@ -38,7 +38,7 @@ where
 	Self: FloatToInt<u32> + FloatToInt<i32>,
 	Self: FloatToInt<u16> + FloatToInt<i16>,
 	Self: FloatToInt<u8> + FloatToInt<i8>,
-	Self: Debug + LowerExp + UpperExp + Display,
+	Self: Debug,
 	Self: Add<Output = Self> + AddAssign,
 	Self: Sub<Output = Self> + SubAssign,
 	Self: Mul<Output = Self> + MulAssign,
diff --git a/src/simd_bits/mod.rs b/src/simd_bits/mod.rs
index 27b0605..99e414b 100644
--- a/src/simd_bits/mod.rs
+++ b/src/simd_bits/mod.rs
@@ -6,7 +6,7 @@
 
 use super::{Bits, Select, SimdMask};
 use core::{
-	fmt::{Debug, Octal},
+	fmt::Debug,
 	hash::Hash,
 	iter::{Product, Sum},
 	ops::{Add, AddAssign, Div, DivAssign, Mul, MulAssign, Rem, RemAssign, Sub, SubAssign},
@@ -33,7 +33,7 @@ where
 	Self: Product<Self> + Sum<Self>,
 	for<'a> Self: Product<&'a Self> + Sum<&'a Self>,
 	Self: Hash,
-	Self: Debug + Octal,
+	Self: Debug,
 	Self: Index<usize, Output = B> + IndexMut<usize, Output = B>,
 	Self: Select<Self::Mask>,
 	Self: Add<Output = Self> + AddAssign,
diff --git a/src/simd_real/mod.rs b/src/simd_real/mod.rs
index 143cc2f..260ed50 100644
--- a/src/simd_real/mod.rs
+++ b/src/simd_real/mod.rs
@@ -8,7 +8,7 @@
 
 use super::{ApproxEq, Real, Select, SimdBits, SimdMask};
 use core::{
-	fmt::{Debug, LowerExp, UpperExp},
+	fmt::Debug,
 	iter::{Product, Sum},
 	ops::{Add, AddAssign, Div, DivAssign, Mul, MulAssign, Neg, Rem, RemAssign, Sub, SubAssign},
 	ops::{Index, IndexMut},
@@ -62,7 +62,7 @@ where
 	LaneCount<LANES>: SupportedLaneCount,
 	Self: Send + Sync + Clone + Copy + Default,
 	Self: ApproxEq<R, Self> + PartialEq + PartialOrd,
-	Self: Debug + LowerExp + UpperExp,
+	Self: Debug,
 	Self: From<Simd<R, LANES>> + Into<Simd<R, LANES>>,
 	Self: From<[R; LANES]> + Into<[R; LANES]>,
 	Self: AsRef<[R; LANES]> + AsMut<[R; LANES]>,