Supplemental technology files for ASAP7 PDK with Synopsys design flow

Supplemental technology files for ASAP7 PDK with Synopsys design flow

一个 密钥检测/密钥分享/密钥查询/获取CID等微软产品激活 相关的小工具，小巧方便

The Prince lightweight block cipher in Verilog.

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

🗂️A file list/WebDAV program that supports multiple storages, powered by Gin and Solidjs. / 一个支持多存储的文件列表/WebDAV程序，使用 Gin 和 Solidjs。

Verilog IP Cores & Tests

Pipeline FFT Implementation in Verilog HDL

Pipelined FFT/IFFT 64 points processor

USB 1.1 PHY (VHDL)

Pipelined FFT/IFFT 128 points processor

Asynchronous WISHBONE-compatible SDRAM controller

A 32 point radix-2 FFT module written in Verilog

PID controller

Verilog CAN controller that is compatible to the SJA 1000.

CAN Protocol Controller

OpenPiton Design Benchmark

An CAN bus Controller implemented in Verilog

PNG encoder, implemented in VHDL

JPEG Encoder Verilog

Reed Solomon Encoder and Decoder Digital IP

A simple JPEG2000 hardware encoder

Verilog Implementation of Run Length Encoding for RGB Image Compression

DVB-S2 LDPC Decoder

This project is being developed as part of a Master's degree research sponsored by Brazil's CNPQ. It's goal is to design a hardware architecture to accelerate the AV1 arithmetic encoder.

Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source

Motorola Chip 6800 CPU Family HDL

Cycle accurate MC6502 compatible processor in Verilog.

tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.