hw: Block SSR reads during write streams

hw/snitch_ssr/src/snitch_ssr.sv

@@ -33,6 +33,7 @@ module snitch_ssr import snitch_ssr_pkg::*; #(
   // Register lanes from switch.
   output data_t       lane_rdata_o,
   input  data_t       lane_wdata_i,
+  input  logic        lane_write_i,
   output logic        lane_valid_o,
   input  logic        lane_ready_i,
   // Ports into memory.
@@ -158,9 +159,13 @@ module snitch_ssr import snitch_ssr_pkg::*; #(
 
   always_comb begin
     if (dm_write) begin
-      lane_valid_o = ~fifo_full;
+      // Accept only writes and only when there is space in the FIFO.
+      // Note this blocks read accesses until the current write stream is over;
+      // This means that reads in the midst of write streams are *deadlocking*
+      // just like excess reads past finished read streams are.
+      lane_valid_o = lane_write_i & ~fifo_full;
       data_req_qvalid = agen_valid & ~fifo_empty & has_credit & ~agen_flush;
-      fifo_push = lane_ready_i & ~fifo_full;
+      fifo_push = lane_valid_o & lane_ready_i;
       fifo_in = lane_wdata_i;
       rep_enable = 0;
       fifo_pop = data_req_qvalid & data_rsp.q_ready;

hw/snitch_ssr/src/snitch_ssr_streamer.sv

@@ -155,6 +155,7 @@ module snitch_ssr_streamer import snitch_ssr_pkg::*; #(
       .cfg_wready_o   ( dmcfg_wready [i]  ),
       .lane_rdata_o   ( lane_rdata   [i]  ),
       .lane_wdata_i   ( lane_wdata   [i]  ),
+      .lane_write_i   ( lane_write   [i]  ),
       .lane_valid_o   ( lane_valid   [i]  ),
       .lane_ready_i   ( lane_ready   [i]  ),
       .mem_req_o      ( mem_req_o    [i]  ),

hw/snitch_ssr/test/fixture_ssr.sv

@@ -102,6 +102,7 @@ module fixture_ssr import snitch_ssr_pkg::*; #(
   tcdm_rsp_t    mem_rsp_i;
   logic [DataWidth-1:0] lane_rdata_o;
   logic [DataWidth-1:0] lane_wdata_i;
+  logic [DataWidth-1:0] lane_write_i;
   logic [AddrWidth-1:0] tcdm_start_address_i = '0;    // (currently) required for test flow
 
   // Device Under Test (DUT)
@@ -126,6 +127,7 @@ module fixture_ssr import snitch_ssr_pkg::*; #(
     .cfg_wready_o,
     .lane_rdata_o,
     .lane_wdata_i,
+    .lane_write_i,
     .lane_valid_o,
     .lane_ready_i,
     .mem_req_o,
@@ -304,6 +306,7 @@ module fixture_ssr import snitch_ssr_pkg::*; #(
 
   // Swap valid and ready to emulate 3-way handshake
   assign lane_wdata_i   = ssr_bus.wdata;
+  assign lane_write_i   = ssr_bus.write;
   assign lane_ready_i   = ssr_bus.valid;
   assign ssr_bus.rdata  = lane_rdata_o;
   assign ssr_bus.ready  = lane_valid_o;