diff --git a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv index 747e79f86c..a931a5e9a4 100644 --- a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv +++ b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv @@ -111,8 +111,9 @@ module snitch_cluster_peripheral IcacheStall }; - logic [NumPerfCounters-1:0][47:0] perf_counter_d, perf_counter_q; + logic [NumPerfCounters-1:0][47:0] perf_cnt_q, perf_cnt_d; perf_metrics_e [NumPerfCounters-1:0] perf_metrics_q, perf_metrics_d; + logic [NumPerfCounters-1:0][$clog2(NrCores)-1:0] perf_hart_sel_q, perf_hart_sel_d; logic [31:0] cl_clint_d, cl_clint_q; // Wake-up logic: Bits in cl_clint_q can be set/cleared with writes to @@ -133,8 +134,9 @@ module snitch_cluster_peripheral // Continuously assign the perf values. for (genvar i = 0; i < NumPerfCounters; i++) begin : gen_perf_assign - assign hw2reg.perf_counter[i].d = perf_counter_q[i]; - assign hw2reg.perf_counter_select[i].d = perf_metrics_q[i]; + assign hw2reg.perf_cnt[i].d = perf_cnt_q[i]; + assign hw2reg.perf_cnt_sel[i].metric.d = perf_metrics_q[i]; + assign hw2reg.perf_cnt_sel[i].hart.d = perf_hart_sel_q[i]; end // The hardware barrier is external and always reads `0`. @@ -142,53 +144,63 @@ module snitch_cluster_peripheral always_comb begin perf_metrics_d = perf_metrics_q; + perf_hart_sel_d = perf_hart_sel_q; for (int i = 0; i < NumPerfCounters; i++) begin automatic core_events_t sel_core_events; automatic logic [$clog2(NrCores)-1:0] hart_select; - hart_select = reg2hw.perf_counter_hart_select[i].q[$clog2(NrCores):0]; + hart_select = reg2hw.perf_cnt_sel[i].hart.q[$clog2(NrCores):0]; sel_core_events = core_events_i[hart_select]; unique case (perf_metrics_q[i]) - Cycle: perf_counter_d[i] += 1; - TcdmAccessed: perf_counter_d[i] += tcdm_events_q.inc_accessed; - TcdmCongested: perf_counter_d[i] += tcdm_events_q.inc_congested; - IssueFpu: perf_counter_d[i] += sel_core_events.issue_fpu; - IssueFpuSeq: perf_counter_d[i] += sel_core_events.issue_fpu_seq; - IssueCoreToFpu: perf_counter_d[i] += sel_core_events.issue_core_to_fpu; - RetiredInstr: perf_counter_d[i] += sel_core_events.retired_instr; - RetiredLoad: perf_counter_d[i] += sel_core_events.retired_load; - RetiredI: perf_counter_d[i] += sel_core_events.retired_i; - RetiredAcc: perf_counter_d[i] += sel_core_events.retired_acc; - DmaAwStall: perf_counter_d[i] += dma_events_q.aw_stall; - DmaArStall: perf_counter_d[i] += dma_events_q.ar_stall; - DmaRStall: perf_counter_d[i] += dma_events_q.r_stall; - DmaWStall: perf_counter_d[i] += dma_events_q.w_stall; - DmaBufWStall: perf_counter_d[i] += dma_events_q.buf_w_stall; - DmaBufRStall: perf_counter_d[i] += dma_events_q.buf_r_stall; - DmaAwDone: perf_counter_d[i] += dma_events_q.aw_done; - DmaAwBw: perf_counter_d[i] += ((dma_events_q.aw_len + 1) << (dma_events_q.aw_size)); - DmaArDone: perf_counter_d[i] += dma_events_q.ar_done; - DmaArBw: perf_counter_d[i] += ((dma_events_q.ar_len + 1) << (dma_events_q.ar_size)); - DmaRDone: perf_counter_d[i] += dma_events_q.r_done; - DmaRBw: perf_counter_d[i] += DMADataWidth/8; - DmaWDone: perf_counter_d[i] += dma_events_q.w_done; - DmaWBw: perf_counter_d[i] += dma_events_q.num_bytes_written; - DmaBDone: perf_counter_d[i] += dma_events_q.b_done; - DmaBusy: perf_counter_d[i] += dma_events_q.dma_busy; - IcacheMiss: perf_counter_d[i] += icache_events_q[hart_select].l0_miss; - IcacheHit: perf_counter_d[i] += icache_events_q[hart_select].l0_hit; - IcachePrefetch: perf_counter_d[i] += icache_events_q[hart_select].l0_prefetch; - IcacheDoubleHit: perf_counter_d[i] += icache_events_q[hart_select].l0_double_hit; - IcacheStall: perf_counter_d[i] += icache_events_q[hart_select].l0_stall; - default: perf_counter_d[i] = perf_counter_q[i]; + Cycle: perf_cnt_d[i] += 1; + TcdmAccessed: perf_cnt_d[i] += tcdm_events_q.inc_accessed; + TcdmCongested: perf_cnt_d[i] += tcdm_events_q.inc_congested; + IssueFpu: perf_cnt_d[i] += sel_core_events.issue_fpu; + IssueFpuSeq: perf_cnt_d[i] += sel_core_events.issue_fpu_seq; + IssueCoreToFpu: perf_cnt_d[i] += sel_core_events.issue_core_to_fpu; + RetiredInstr: perf_cnt_d[i] += sel_core_events.retired_instr; + RetiredLoad: perf_cnt_d[i] += sel_core_events.retired_load; + RetiredI: perf_cnt_d[i] += sel_core_events.retired_i; + RetiredAcc: perf_cnt_d[i] += sel_core_events.retired_acc; + DmaAwStall: perf_cnt_d[i] += dma_events_q.aw_stall; + DmaArStall: perf_cnt_d[i] += dma_events_q.ar_stall; + DmaRStall: perf_cnt_d[i] += dma_events_q.r_stall; + DmaWStall: perf_cnt_d[i] += dma_events_q.w_stall; + DmaBufWStall: perf_cnt_d[i] += dma_events_q.buf_w_stall; + DmaBufRStall: perf_cnt_d[i] += dma_events_q.buf_r_stall; + DmaAwDone: perf_cnt_d[i] += dma_events_q.aw_done; + DmaAwBw: perf_cnt_d[i] += ((dma_events_q.aw_len + 1) << (dma_events_q.aw_size)); + DmaArDone: perf_cnt_d[i] += dma_events_q.ar_done; + DmaArBw: perf_cnt_d[i] += ((dma_events_q.ar_len + 1) << (dma_events_q.ar_size)); + DmaRDone: perf_cnt_d[i] += dma_events_q.r_done; + DmaRBw: perf_cnt_d[i] += DMADataWidth/8; + DmaWDone: perf_cnt_d[i] += dma_events_q.w_done; + DmaWBw: perf_cnt_d[i] += dma_events_q.num_bytes_written; + DmaBDone: perf_cnt_d[i] += dma_events_q.b_done; + DmaBusy: perf_cnt_d[i] += dma_events_q.dma_busy; + IcacheMiss: perf_cnt_d[i] += icache_events_q[hart_select].l0_miss; + IcacheHit: perf_cnt_d[i] += icache_events_q[hart_select].l0_hit; + IcachePrefetch: perf_cnt_d[i] += icache_events_q[hart_select].l0_prefetch; + IcacheDoubleHit: perf_cnt_d[i] += icache_events_q[hart_select].l0_double_hit; + IcacheStall: perf_cnt_d[i] += icache_events_q[hart_select].l0_stall; + default: perf_cnt_d[i] = perf_cnt_q[i]; endcase // Reset performance counter. - if (reg2hw.perf_counter[i].qe) begin - perf_counter_d[i] = reg2hw.perf_counter[i].q; + if (reg2hw.perf_cnt[i].qe) begin + perf_cnt_d[i] = reg2hw.perf_cnt[i].q; + end + // Set performance metric. + if (reg2hw.perf_cnt_sel[i].metric.qe) begin + perf_metrics_d[i] = perf_metrics_e'(reg2hw.perf_cnt_sel[i].metric.q); + end + // Set hart select. + if (reg2hw.perf_cnt_sel[i].hart.qe) begin + perf_hart_sel_d[i] = reg2hw.perf_cnt_sel[i].hart.q; end end end - `FF(perf_counter_q, perf_counter_d, '0, clk_i, rst_ni) + // Actual performance counters. + `FF(perf_cnt_q, perf_cnt_d, '0, clk_i, rst_ni) // Set reset values for the metrics that should be tracked immediately after reset. for (genvar i = 0; i < NumPerfCounters; i++) begin : gen_perf_metrics_assign @@ -199,4 +211,7 @@ module snitch_cluster_peripheral end end + // Use hart `0` as default. + `FF(perf_hart_sel_q, perf_hart_sel_d, 0, clk_i, rst_ni) + endmodule diff --git a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson index 274b50d761..f875fd32b5 100644 --- a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson +++ b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson @@ -19,7 +19,7 @@ registers: [ { multireg: { - name: "PERF_COUNTER_ENABLE", + name: "PERF_CNT_EN", desc: "Enable a particular performance counter to start tracking." swaccess: "rw", hwaccess: "hro", @@ -28,24 +28,34 @@ compact: "false", fields: [{ bits: "0:0", - name: "PERF_COUNTER_ENABLE", - desc: "Enable performance counter" + name: "ENABLE", + desc: "Enable a particular performance counter to start tracking." }] } }, { multireg: { - name: "PERF_COUNTER_SELECT", + name: "PERF_CNT_SEL", desc: "Select the metric that is tracked for each performance counter.", swaccess: "rw", hwaccess: "hrw", count: "NumPerfCounters", cname: "perf_cnt_sel", - compact: "false", hwext: "true", hwqe: "true", fields: [{ - bits: "9:0", name: "PERF_COUNTER_SELECT", + bits: "15:0", + name: "HART", + desc: '''Select from which hart in the cluster, starting from `0`, + the event should be counted. For each performance counter + the cores can be selected individually. If a hart greater + than the clusters total hart size is selected the selection + will wrap and the hart corresponding to `hart_select % total_harts_in_cluster` + will be selected.''' + }, + { + bits: "31:16", + name: "METRIC", desc: "Select the metric that is tracked for each performance counter", enum: [{ value: "0", @@ -276,34 +286,13 @@ }, { multireg: { - name: "PERF_COUNTER_HART_SELECT", - desc: '''Select from which hart in the cluster, starting from `0`, - the event should be counted. For each performance counter - the cores can be selected individually. If a hart greater - than the clusters total hart size is selected the selection - will wrap and the hart corresponding to `hart_select % total_harts_in_cluster` - will be selected.''' - swaccess: "rw", - hwaccess: "hro", - count: "NumPerfCounters", - cname: "perf_cnt_hart_select", - compact: "false", - fields: [{ - bits: "9:0", - name: "PERF_COUNTER_HART_SELECT", - desc: "Select source of per-hart performance counter" - }] - } - } - { - multireg: { - name: "PERF_COUNTER", + name: "PERF_CNT", desc: '''Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending on what performance metric you would like to track.''' swaccess: "rw", hwaccess: "hrw", count: "NumPerfCounters", - cname: "performance_counter", + cname: "perf_cnt", hwext: "true", hwqe: "true", fields: [{ diff --git a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv index 1ceb99974c..9d096e5bd2 100644 --- a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv +++ b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv @@ -10,27 +10,29 @@ package snitch_cluster_peripheral_reg_pkg; parameter int NumPerfCounters = 16; // Address widths within the block - parameter int BlockAw = 10; + parameter int BlockAw = 9; //////////////////////////// // Typedefs for registers // //////////////////////////// - typedef struct packed {logic q;} snitch_cluster_peripheral_reg2hw_perf_counter_enable_mreg_t; + typedef struct packed {logic q;} snitch_cluster_peripheral_reg2hw_perf_cnt_en_mreg_t; typedef struct packed { - logic [9:0] q; - logic qe; - } snitch_cluster_peripheral_reg2hw_perf_counter_select_mreg_t; - - typedef struct packed { - logic [9:0] q; - } snitch_cluster_peripheral_reg2hw_perf_counter_hart_select_mreg_t; + struct packed { + logic [15:0] q; + logic qe; + } hart; + struct packed { + logic [15:0] q; + logic qe; + } metric; + } snitch_cluster_peripheral_reg2hw_perf_cnt_sel_mreg_t; typedef struct packed { logic [47:0] q; logic qe; - } snitch_cluster_peripheral_reg2hw_perf_counter_mreg_t; + } snitch_cluster_peripheral_reg2hw_perf_cnt_mreg_t; typedef struct packed { logic [31:0] q; @@ -47,19 +49,19 @@ package snitch_cluster_peripheral_reg_pkg; typedef struct packed {logic q;} snitch_cluster_peripheral_reg2hw_icache_prefetch_enable_reg_t; typedef struct packed { - logic [9:0] d; - } snitch_cluster_peripheral_hw2reg_perf_counter_select_mreg_t; + struct packed {logic [15:0] d;} hart; + struct packed {logic [15:0] d;} metric; + } snitch_cluster_peripheral_hw2reg_perf_cnt_sel_mreg_t; - typedef struct packed {logic [47:0] d;} snitch_cluster_peripheral_hw2reg_perf_counter_mreg_t; + typedef struct packed {logic [47:0] d;} snitch_cluster_peripheral_hw2reg_perf_cnt_mreg_t; typedef struct packed {logic [31:0] d;} snitch_cluster_peripheral_hw2reg_hw_barrier_reg_t; // Register -> HW type typedef struct packed { - snitch_cluster_peripheral_reg2hw_perf_counter_enable_mreg_t [15:0] perf_counter_enable; // [1234:1219] - snitch_cluster_peripheral_reg2hw_perf_counter_select_mreg_t [15:0] perf_counter_select; // [1218:1043] - snitch_cluster_peripheral_reg2hw_perf_counter_hart_select_mreg_t [15:0] perf_counter_hart_select; // [1042:883] - snitch_cluster_peripheral_reg2hw_perf_counter_mreg_t [15:0] perf_counter; // [882:99] + snitch_cluster_peripheral_reg2hw_perf_cnt_en_mreg_t [15:0] perf_cnt_en; // [1442:1427] + snitch_cluster_peripheral_reg2hw_perf_cnt_sel_mreg_t [15:0] perf_cnt_sel; // [1426:883] + snitch_cluster_peripheral_reg2hw_perf_cnt_mreg_t [15:0] perf_cnt; // [882:99] snitch_cluster_peripheral_reg2hw_cl_clint_set_reg_t cl_clint_set; // [98:66] snitch_cluster_peripheral_reg2hw_cl_clint_clear_reg_t cl_clint_clear; // [65:33] snitch_cluster_peripheral_reg2hw_hw_barrier_reg_t hw_barrier; // [32:1] @@ -68,184 +70,152 @@ package snitch_cluster_peripheral_reg_pkg; // HW -> register type typedef struct packed { - snitch_cluster_peripheral_hw2reg_perf_counter_select_mreg_t [15:0] perf_counter_select; // [959:800] - snitch_cluster_peripheral_hw2reg_perf_counter_mreg_t [15:0] perf_counter; // [799:32] + snitch_cluster_peripheral_hw2reg_perf_cnt_sel_mreg_t [15:0] perf_cnt_sel; // [1311:800] + snitch_cluster_peripheral_hw2reg_perf_cnt_mreg_t [15:0] perf_cnt; // [799:32] snitch_cluster_peripheral_hw2reg_hw_barrier_reg_t hw_barrier; // [31:0] } snitch_cluster_peripheral_hw2reg_t; // Register offsets - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_OFFSET = 10'h0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_OFFSET = 10'h8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_OFFSET = 10'h10; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_OFFSET = 10'h18; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_OFFSET = 10'h20; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_OFFSET = 10'h28; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_OFFSET = 10'h30; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_OFFSET = 10'h38; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_OFFSET = 10'h40; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_OFFSET = 10'h48; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_OFFSET = 10'h50; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_OFFSET = 10'h58; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_OFFSET = 10'h60; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_OFFSET = 10'h68; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_OFFSET = 10'h70; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_OFFSET = 10'h78; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_0_OFFSET = 10'h80; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_1_OFFSET = 10'h88; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_2_OFFSET = 10'h90; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_3_OFFSET = 10'h98; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_4_OFFSET = 10'ha0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_5_OFFSET = 10'ha8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_6_OFFSET = 10'hb0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_7_OFFSET = 10'hb8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_8_OFFSET = 10'hc0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_9_OFFSET = 10'hc8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_10_OFFSET = 10'hd0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_11_OFFSET = 10'hd8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_12_OFFSET = 10'he0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_13_OFFSET = 10'he8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_14_OFFSET = 10'hf0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_15_OFFSET = 10'hf8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_0_OFFSET = 10'h 100; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_1_OFFSET = 10'h 108; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_2_OFFSET = 10'h 110; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_3_OFFSET = 10'h 118; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_4_OFFSET = 10'h 120; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_5_OFFSET = 10'h 128; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_6_OFFSET = 10'h 130; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_7_OFFSET = 10'h 138; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_8_OFFSET = 10'h 140; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_9_OFFSET = 10'h 148; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_10_OFFSET = 10'h 150; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_11_OFFSET = 10'h 158; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_12_OFFSET = 10'h 160; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_13_OFFSET = 10'h 168; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_14_OFFSET = 10'h 170; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_15_OFFSET = 10'h 178; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_0_OFFSET = 10'h180; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_1_OFFSET = 10'h188; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_2_OFFSET = 10'h190; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_3_OFFSET = 10'h198; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_4_OFFSET = 10'h1a0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_5_OFFSET = 10'h1a8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_6_OFFSET = 10'h1b0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_7_OFFSET = 10'h1b8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_8_OFFSET = 10'h1c0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_9_OFFSET = 10'h1c8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_10_OFFSET = 10'h1d0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_11_OFFSET = 10'h1d8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_12_OFFSET = 10'h1e0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_13_OFFSET = 10'h1e8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_14_OFFSET = 10'h1f0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_15_OFFSET = 10'h1f8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_OFFSET = 10'h200; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_OFFSET = 10'h208; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_OFFSET = 10'h210; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET = 10'h218; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0_OFFSET = 9'h0; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_1_OFFSET = 9'h8; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_2_OFFSET = 9'h10; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_3_OFFSET = 9'h18; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_4_OFFSET = 9'h20; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_5_OFFSET = 9'h28; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_6_OFFSET = 9'h30; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_7_OFFSET = 9'h38; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_8_OFFSET = 9'h40; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_9_OFFSET = 9'h48; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_10_OFFSET = 9'h50; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_11_OFFSET = 9'h58; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_12_OFFSET = 9'h60; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_13_OFFSET = 9'h68; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_14_OFFSET = 9'h70; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_15_OFFSET = 9'h78; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_OFFSET = 9'h80; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_1_OFFSET = 9'h88; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_2_OFFSET = 9'h90; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_3_OFFSET = 9'h98; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_4_OFFSET = 9'ha0; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_5_OFFSET = 9'ha8; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_6_OFFSET = 9'hb0; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_7_OFFSET = 9'hb8; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_8_OFFSET = 9'hc0; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_9_OFFSET = 9'hc8; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_10_OFFSET = 9'hd0; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_11_OFFSET = 9'hd8; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_12_OFFSET = 9'he0; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_13_OFFSET = 9'he8; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_14_OFFSET = 9'hf0; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_15_OFFSET = 9'hf8; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_0_OFFSET = 9'h100; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_1_OFFSET = 9'h108; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_2_OFFSET = 9'h110; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_3_OFFSET = 9'h118; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_4_OFFSET = 9'h120; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_5_OFFSET = 9'h128; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_6_OFFSET = 9'h130; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_7_OFFSET = 9'h138; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_8_OFFSET = 9'h140; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_9_OFFSET = 9'h148; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_10_OFFSET = 9'h150; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_11_OFFSET = 9'h158; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_12_OFFSET = 9'h160; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13_OFFSET = 9'h168; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14_OFFSET = 9'h170; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15_OFFSET = 9'h178; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_OFFSET = 9'h180; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_OFFSET = 9'h188; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_OFFSET = 9'h190; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET = 9'h198; // Reset values for hwext registers and their fields - parameter logic [9:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_0_RESVAL = 10'h0; - parameter logic [9:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_1_RESVAL = 10'h0; - parameter logic [9:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_2_RESVAL = 10'h0; - parameter logic [9:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_3_RESVAL = 10'h0; - parameter logic [9:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_4_RESVAL = 10'h0; - parameter logic [9:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_5_RESVAL = 10'h0; - parameter logic [9:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_6_RESVAL = 10'h0; - parameter logic [9:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_7_RESVAL = 10'h0; - parameter logic [9:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_8_RESVAL = 10'h0; - parameter logic [9:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_9_RESVAL = 10'h0; - parameter logic [9:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_10_RESVAL = 10'h0; - parameter logic [9:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_11_RESVAL = 10'h0; - parameter logic [9:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_12_RESVAL = 10'h0; - parameter logic [9:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_13_RESVAL = 10'h0; - parameter logic [9:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_14_RESVAL = 10'h0; - parameter logic [9:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_15_RESVAL = 10'h0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_0_RESVAL = 48'h0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_1_RESVAL = 48'h0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_2_RESVAL = 48'h0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_3_RESVAL = 48'h0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_4_RESVAL = 48'h0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_5_RESVAL = 48'h0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_6_RESVAL = 48'h0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_7_RESVAL = 48'h0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_8_RESVAL = 48'h0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_9_RESVAL = 48'h0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_10_RESVAL = 48'h0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_11_RESVAL = 48'h0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_12_RESVAL = 48'h0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_13_RESVAL = 48'h0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_14_RESVAL = 48'h0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_15_RESVAL = 48'h0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_RESVAL = 32'h0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_1_RESVAL = 32'h0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_2_RESVAL = 32'h0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_3_RESVAL = 32'h0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_4_RESVAL = 32'h0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_5_RESVAL = 32'h0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_6_RESVAL = 32'h0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_7_RESVAL = 32'h0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_8_RESVAL = 32'h0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_9_RESVAL = 32'h0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_10_RESVAL = 32'h0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_11_RESVAL = 32'h0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_12_RESVAL = 32'h0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_13_RESVAL = 32'h0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_14_RESVAL = 32'h0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_15_RESVAL = 32'h0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_0_RESVAL = 48'h0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_1_RESVAL = 48'h0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_2_RESVAL = 48'h0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_3_RESVAL = 48'h0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_4_RESVAL = 48'h0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_5_RESVAL = 48'h0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_6_RESVAL = 48'h0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_7_RESVAL = 48'h0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_8_RESVAL = 48'h0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_9_RESVAL = 48'h0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_10_RESVAL = 48'h0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_11_RESVAL = 48'h0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_12_RESVAL = 48'h0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13_RESVAL = 48'h0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14_RESVAL = 48'h0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15_RESVAL = 48'h0; parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_RESVAL = 32'h0; parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_RESVAL = 32'h0; parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_RESVAL = 32'h0; // Register index typedef enum int { - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_0, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_1, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_2, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_3, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_4, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_5, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_6, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_7, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_8, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_9, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_10, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_11, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_12, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_13, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_14, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_15, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_0, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_1, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_2, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_3, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_4, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_5, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_6, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_7, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_8, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_9, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_10, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_11, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_12, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_13, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_14, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_15, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_0, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_1, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_2, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_3, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_4, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_5, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_6, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_7, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_8, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_9, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_10, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_11, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_12, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_13, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_14, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_15, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_1, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_2, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_3, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_4, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_5, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_6, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_7, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_8, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_9, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_10, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_11, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_12, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_13, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_14, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_15, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_1, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_2, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_3, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_4, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_5, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_6, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_7, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_8, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_9, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_10, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_11, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_12, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_13, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_14, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_15, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_0, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_1, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_2, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_3, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_4, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_5, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_6, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_7, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_8, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_9, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_10, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_11, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_12, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15, SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET, SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR, SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER, @@ -253,75 +223,59 @@ package snitch_cluster_peripheral_reg_pkg; } snitch_cluster_peripheral_id_e; // Register width information to check illegal writes - parameter logic [3:0] SNITCH_CLUSTER_PERIPHERAL_PERMIT[68] = '{ - 4'b0001, // index[ 0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0 - 4'b0001, // index[ 1] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1 - 4'b0001, // index[ 2] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2 - 4'b0001, // index[ 3] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3 - 4'b0001, // index[ 4] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4 - 4'b0001, // index[ 5] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5 - 4'b0001, // index[ 6] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6 - 4'b0001, // index[ 7] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7 - 4'b0001, // index[ 8] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8 - 4'b0001, // index[ 9] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9 - 4'b0001, // index[10] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10 - 4'b0001, // index[11] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11 - 4'b0001, // index[12] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12 - 4'b0001, // index[13] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13 - 4'b0001, // index[14] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14 - 4'b0001, // index[15] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15 - 4'b0011, // index[16] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_0 - 4'b0011, // index[17] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_1 - 4'b0011, // index[18] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_2 - 4'b0011, // index[19] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_3 - 4'b0011, // index[20] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_4 - 4'b0011, // index[21] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_5 - 4'b0011, // index[22] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_6 - 4'b0011, // index[23] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_7 - 4'b0011, // index[24] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_8 - 4'b0011, // index[25] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_9 - 4'b0011, // index[26] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_10 - 4'b0011, // index[27] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_11 - 4'b0011, // index[28] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_12 - 4'b0011, // index[29] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_13 - 4'b0011, // index[30] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_14 - 4'b0011, // index[31] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_15 - 4'b0011, // index[32] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_0 - 4'b0011, // index[33] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_1 - 4'b0011, // index[34] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_2 - 4'b0011, // index[35] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_3 - 4'b0011, // index[36] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_4 - 4'b0011, // index[37] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_5 - 4'b0011, // index[38] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_6 - 4'b0011, // index[39] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_7 - 4'b0011, // index[40] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_8 - 4'b0011, // index[41] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_9 - 4'b0011, // index[42] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_10 - 4'b0011, // index[43] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_11 - 4'b0011, // index[44] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_12 - 4'b0011, // index[45] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_13 - 4'b0011, // index[46] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_14 - 4'b0011, // index[47] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_15 - 4'b1111, // index[48] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_0 - 4'b1111, // index[49] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_1 - 4'b1111, // index[50] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_2 - 4'b1111, // index[51] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_3 - 4'b1111, // index[52] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_4 - 4'b1111, // index[53] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_5 - 4'b1111, // index[54] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_6 - 4'b1111, // index[55] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_7 - 4'b1111, // index[56] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_8 - 4'b1111, // index[57] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_9 - 4'b1111, // index[58] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_10 - 4'b1111, // index[59] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_11 - 4'b1111, // index[60] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_12 - 4'b1111, // index[61] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_13 - 4'b1111, // index[62] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_14 - 4'b1111, // index[63] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_15 - 4'b1111, // index[64] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET - 4'b1111, // index[65] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR - 4'b1111, // index[66] SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER - 4'b0001 // index[67] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE + parameter logic [3:0] SNITCH_CLUSTER_PERIPHERAL_PERMIT[52] = '{ + 4'b0001, // index[ 0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0 + 4'b0001, // index[ 1] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_1 + 4'b0001, // index[ 2] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_2 + 4'b0001, // index[ 3] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_3 + 4'b0001, // index[ 4] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_4 + 4'b0001, // index[ 5] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_5 + 4'b0001, // index[ 6] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_6 + 4'b0001, // index[ 7] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_7 + 4'b0001, // index[ 8] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_8 + 4'b0001, // index[ 9] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_9 + 4'b0001, // index[10] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_10 + 4'b0001, // index[11] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_11 + 4'b0001, // index[12] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_12 + 4'b0001, // index[13] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_13 + 4'b0001, // index[14] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_14 + 4'b0001, // index[15] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_15 + 4'b1111, // index[16] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0 + 4'b1111, // index[17] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_1 + 4'b1111, // index[18] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_2 + 4'b1111, // index[19] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_3 + 4'b1111, // index[20] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_4 + 4'b1111, // index[21] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_5 + 4'b1111, // index[22] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_6 + 4'b1111, // index[23] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_7 + 4'b1111, // index[24] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_8 + 4'b1111, // index[25] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_9 + 4'b1111, // index[26] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_10 + 4'b1111, // index[27] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_11 + 4'b1111, // index[28] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_12 + 4'b1111, // index[29] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_13 + 4'b1111, // index[30] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_14 + 4'b1111, // index[31] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_15 + 4'b1111, // index[32] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_0 + 4'b1111, // index[33] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_1 + 4'b1111, // index[34] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_2 + 4'b1111, // index[35] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_3 + 4'b1111, // index[36] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_4 + 4'b1111, // index[37] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_5 + 4'b1111, // index[38] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_6 + 4'b1111, // index[39] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_7 + 4'b1111, // index[40] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_8 + 4'b1111, // index[41] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_9 + 4'b1111, // index[42] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_10 + 4'b1111, // index[43] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_11 + 4'b1111, // index[44] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_12 + 4'b1111, // index[45] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13 + 4'b1111, // index[46] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14 + 4'b1111, // index[47] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15 + 4'b1111, // index[48] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET + 4'b1111, // index[49] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR + 4'b1111, // index[50] SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER + 4'b0001 // index[51] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE }; endpackage diff --git a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv index 5547675246..14ffdc02ef 100644 --- a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv +++ b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv @@ -10,7 +10,7 @@ module snitch_cluster_peripheral_reg_top #( parameter type reg_req_t = logic, parameter type reg_rsp_t = logic, - parameter int AW = 10 + parameter int AW = 9 ) ( input logic clk_i, input logic rst_ni, @@ -68,230 +68,246 @@ module snitch_cluster_peripheral_reg_top #( // Define SW related signals // Format: __{wd|we|qs} // or _{wd|we|qs} if field == 1 or 0 - logic perf_counter_enable_0_qs; - logic perf_counter_enable_0_wd; - logic perf_counter_enable_0_we; - logic perf_counter_enable_1_qs; - logic perf_counter_enable_1_wd; - logic perf_counter_enable_1_we; - logic perf_counter_enable_2_qs; - logic perf_counter_enable_2_wd; - logic perf_counter_enable_2_we; - logic perf_counter_enable_3_qs; - logic perf_counter_enable_3_wd; - logic perf_counter_enable_3_we; - logic perf_counter_enable_4_qs; - logic perf_counter_enable_4_wd; - logic perf_counter_enable_4_we; - logic perf_counter_enable_5_qs; - logic perf_counter_enable_5_wd; - logic perf_counter_enable_5_we; - logic perf_counter_enable_6_qs; - logic perf_counter_enable_6_wd; - logic perf_counter_enable_6_we; - logic perf_counter_enable_7_qs; - logic perf_counter_enable_7_wd; - logic perf_counter_enable_7_we; - logic perf_counter_enable_8_qs; - logic perf_counter_enable_8_wd; - logic perf_counter_enable_8_we; - logic perf_counter_enable_9_qs; - logic perf_counter_enable_9_wd; - logic perf_counter_enable_9_we; - logic perf_counter_enable_10_qs; - logic perf_counter_enable_10_wd; - logic perf_counter_enable_10_we; - logic perf_counter_enable_11_qs; - logic perf_counter_enable_11_wd; - logic perf_counter_enable_11_we; - logic perf_counter_enable_12_qs; - logic perf_counter_enable_12_wd; - logic perf_counter_enable_12_we; - logic perf_counter_enable_13_qs; - logic perf_counter_enable_13_wd; - logic perf_counter_enable_13_we; - logic perf_counter_enable_14_qs; - logic perf_counter_enable_14_wd; - logic perf_counter_enable_14_we; - logic perf_counter_enable_15_qs; - logic perf_counter_enable_15_wd; - logic perf_counter_enable_15_we; - logic [9:0] perf_counter_select_0_qs; - logic [9:0] perf_counter_select_0_wd; - logic perf_counter_select_0_we; - logic perf_counter_select_0_re; - logic [9:0] perf_counter_select_1_qs; - logic [9:0] perf_counter_select_1_wd; - logic perf_counter_select_1_we; - logic perf_counter_select_1_re; - logic [9:0] perf_counter_select_2_qs; - logic [9:0] perf_counter_select_2_wd; - logic perf_counter_select_2_we; - logic perf_counter_select_2_re; - logic [9:0] perf_counter_select_3_qs; - logic [9:0] perf_counter_select_3_wd; - logic perf_counter_select_3_we; - logic perf_counter_select_3_re; - logic [9:0] perf_counter_select_4_qs; - logic [9:0] perf_counter_select_4_wd; - logic perf_counter_select_4_we; - logic perf_counter_select_4_re; - logic [9:0] perf_counter_select_5_qs; - logic [9:0] perf_counter_select_5_wd; - logic perf_counter_select_5_we; - logic perf_counter_select_5_re; - logic [9:0] perf_counter_select_6_qs; - logic [9:0] perf_counter_select_6_wd; - logic perf_counter_select_6_we; - logic perf_counter_select_6_re; - logic [9:0] perf_counter_select_7_qs; - logic [9:0] perf_counter_select_7_wd; - logic perf_counter_select_7_we; - logic perf_counter_select_7_re; - logic [9:0] perf_counter_select_8_qs; - logic [9:0] perf_counter_select_8_wd; - logic perf_counter_select_8_we; - logic perf_counter_select_8_re; - logic [9:0] perf_counter_select_9_qs; - logic [9:0] perf_counter_select_9_wd; - logic perf_counter_select_9_we; - logic perf_counter_select_9_re; - logic [9:0] perf_counter_select_10_qs; - logic [9:0] perf_counter_select_10_wd; - logic perf_counter_select_10_we; - logic perf_counter_select_10_re; - logic [9:0] perf_counter_select_11_qs; - logic [9:0] perf_counter_select_11_wd; - logic perf_counter_select_11_we; - logic perf_counter_select_11_re; - logic [9:0] perf_counter_select_12_qs; - logic [9:0] perf_counter_select_12_wd; - logic perf_counter_select_12_we; - logic perf_counter_select_12_re; - logic [9:0] perf_counter_select_13_qs; - logic [9:0] perf_counter_select_13_wd; - logic perf_counter_select_13_we; - logic perf_counter_select_13_re; - logic [9:0] perf_counter_select_14_qs; - logic [9:0] perf_counter_select_14_wd; - logic perf_counter_select_14_we; - logic perf_counter_select_14_re; - logic [9:0] perf_counter_select_15_qs; - logic [9:0] perf_counter_select_15_wd; - logic perf_counter_select_15_we; - logic perf_counter_select_15_re; - logic [9:0] perf_counter_hart_select_0_qs; - logic [9:0] perf_counter_hart_select_0_wd; - logic perf_counter_hart_select_0_we; - logic [9:0] perf_counter_hart_select_1_qs; - logic [9:0] perf_counter_hart_select_1_wd; - logic perf_counter_hart_select_1_we; - logic [9:0] perf_counter_hart_select_2_qs; - logic [9:0] perf_counter_hart_select_2_wd; - logic perf_counter_hart_select_2_we; - logic [9:0] perf_counter_hart_select_3_qs; - logic [9:0] perf_counter_hart_select_3_wd; - logic perf_counter_hart_select_3_we; - logic [9:0] perf_counter_hart_select_4_qs; - logic [9:0] perf_counter_hart_select_4_wd; - logic perf_counter_hart_select_4_we; - logic [9:0] perf_counter_hart_select_5_qs; - logic [9:0] perf_counter_hart_select_5_wd; - logic perf_counter_hart_select_5_we; - logic [9:0] perf_counter_hart_select_6_qs; - logic [9:0] perf_counter_hart_select_6_wd; - logic perf_counter_hart_select_6_we; - logic [9:0] perf_counter_hart_select_7_qs; - logic [9:0] perf_counter_hart_select_7_wd; - logic perf_counter_hart_select_7_we; - logic [9:0] perf_counter_hart_select_8_qs; - logic [9:0] perf_counter_hart_select_8_wd; - logic perf_counter_hart_select_8_we; - logic [9:0] perf_counter_hart_select_9_qs; - logic [9:0] perf_counter_hart_select_9_wd; - logic perf_counter_hart_select_9_we; - logic [9:0] perf_counter_hart_select_10_qs; - logic [9:0] perf_counter_hart_select_10_wd; - logic perf_counter_hart_select_10_we; - logic [9:0] perf_counter_hart_select_11_qs; - logic [9:0] perf_counter_hart_select_11_wd; - logic perf_counter_hart_select_11_we; - logic [9:0] perf_counter_hart_select_12_qs; - logic [9:0] perf_counter_hart_select_12_wd; - logic perf_counter_hart_select_12_we; - logic [9:0] perf_counter_hart_select_13_qs; - logic [9:0] perf_counter_hart_select_13_wd; - logic perf_counter_hart_select_13_we; - logic [9:0] perf_counter_hart_select_14_qs; - logic [9:0] perf_counter_hart_select_14_wd; - logic perf_counter_hart_select_14_we; - logic [9:0] perf_counter_hart_select_15_qs; - logic [9:0] perf_counter_hart_select_15_wd; - logic perf_counter_hart_select_15_we; - logic [47:0] perf_counter_0_qs; - logic [47:0] perf_counter_0_wd; - logic perf_counter_0_we; - logic perf_counter_0_re; - logic [47:0] perf_counter_1_qs; - logic [47:0] perf_counter_1_wd; - logic perf_counter_1_we; - logic perf_counter_1_re; - logic [47:0] perf_counter_2_qs; - logic [47:0] perf_counter_2_wd; - logic perf_counter_2_we; - logic perf_counter_2_re; - logic [47:0] perf_counter_3_qs; - logic [47:0] perf_counter_3_wd; - logic perf_counter_3_we; - logic perf_counter_3_re; - logic [47:0] perf_counter_4_qs; - logic [47:0] perf_counter_4_wd; - logic perf_counter_4_we; - logic perf_counter_4_re; - logic [47:0] perf_counter_5_qs; - logic [47:0] perf_counter_5_wd; - logic perf_counter_5_we; - logic perf_counter_5_re; - logic [47:0] perf_counter_6_qs; - logic [47:0] perf_counter_6_wd; - logic perf_counter_6_we; - logic perf_counter_6_re; - logic [47:0] perf_counter_7_qs; - logic [47:0] perf_counter_7_wd; - logic perf_counter_7_we; - logic perf_counter_7_re; - logic [47:0] perf_counter_8_qs; - logic [47:0] perf_counter_8_wd; - logic perf_counter_8_we; - logic perf_counter_8_re; - logic [47:0] perf_counter_9_qs; - logic [47:0] perf_counter_9_wd; - logic perf_counter_9_we; - logic perf_counter_9_re; - logic [47:0] perf_counter_10_qs; - logic [47:0] perf_counter_10_wd; - logic perf_counter_10_we; - logic perf_counter_10_re; - logic [47:0] perf_counter_11_qs; - logic [47:0] perf_counter_11_wd; - logic perf_counter_11_we; - logic perf_counter_11_re; - logic [47:0] perf_counter_12_qs; - logic [47:0] perf_counter_12_wd; - logic perf_counter_12_we; - logic perf_counter_12_re; - logic [47:0] perf_counter_13_qs; - logic [47:0] perf_counter_13_wd; - logic perf_counter_13_we; - logic perf_counter_13_re; - logic [47:0] perf_counter_14_qs; - logic [47:0] perf_counter_14_wd; - logic perf_counter_14_we; - logic perf_counter_14_re; - logic [47:0] perf_counter_15_qs; - logic [47:0] perf_counter_15_wd; - logic perf_counter_15_we; - logic perf_counter_15_re; + logic perf_cnt_en_0_qs; + logic perf_cnt_en_0_wd; + logic perf_cnt_en_0_we; + logic perf_cnt_en_1_qs; + logic perf_cnt_en_1_wd; + logic perf_cnt_en_1_we; + logic perf_cnt_en_2_qs; + logic perf_cnt_en_2_wd; + logic perf_cnt_en_2_we; + logic perf_cnt_en_3_qs; + logic perf_cnt_en_3_wd; + logic perf_cnt_en_3_we; + logic perf_cnt_en_4_qs; + logic perf_cnt_en_4_wd; + logic perf_cnt_en_4_we; + logic perf_cnt_en_5_qs; + logic perf_cnt_en_5_wd; + logic perf_cnt_en_5_we; + logic perf_cnt_en_6_qs; + logic perf_cnt_en_6_wd; + logic perf_cnt_en_6_we; + logic perf_cnt_en_7_qs; + logic perf_cnt_en_7_wd; + logic perf_cnt_en_7_we; + logic perf_cnt_en_8_qs; + logic perf_cnt_en_8_wd; + logic perf_cnt_en_8_we; + logic perf_cnt_en_9_qs; + logic perf_cnt_en_9_wd; + logic perf_cnt_en_9_we; + logic perf_cnt_en_10_qs; + logic perf_cnt_en_10_wd; + logic perf_cnt_en_10_we; + logic perf_cnt_en_11_qs; + logic perf_cnt_en_11_wd; + logic perf_cnt_en_11_we; + logic perf_cnt_en_12_qs; + logic perf_cnt_en_12_wd; + logic perf_cnt_en_12_we; + logic perf_cnt_en_13_qs; + logic perf_cnt_en_13_wd; + logic perf_cnt_en_13_we; + logic perf_cnt_en_14_qs; + logic perf_cnt_en_14_wd; + logic perf_cnt_en_14_we; + logic perf_cnt_en_15_qs; + logic perf_cnt_en_15_wd; + logic perf_cnt_en_15_we; + logic [15:0] perf_cnt_sel_0_hart_0_qs; + logic [15:0] perf_cnt_sel_0_hart_0_wd; + logic perf_cnt_sel_0_hart_0_we; + logic perf_cnt_sel_0_hart_0_re; + logic [15:0] perf_cnt_sel_0_metric_0_qs; + logic [15:0] perf_cnt_sel_0_metric_0_wd; + logic perf_cnt_sel_0_metric_0_we; + logic perf_cnt_sel_0_metric_0_re; + logic [15:0] perf_cnt_sel_1_hart_1_qs; + logic [15:0] perf_cnt_sel_1_hart_1_wd; + logic perf_cnt_sel_1_hart_1_we; + logic perf_cnt_sel_1_hart_1_re; + logic [15:0] perf_cnt_sel_1_metric_1_qs; + logic [15:0] perf_cnt_sel_1_metric_1_wd; + logic perf_cnt_sel_1_metric_1_we; + logic perf_cnt_sel_1_metric_1_re; + logic [15:0] perf_cnt_sel_2_hart_2_qs; + logic [15:0] perf_cnt_sel_2_hart_2_wd; + logic perf_cnt_sel_2_hart_2_we; + logic perf_cnt_sel_2_hart_2_re; + logic [15:0] perf_cnt_sel_2_metric_2_qs; + logic [15:0] perf_cnt_sel_2_metric_2_wd; + logic perf_cnt_sel_2_metric_2_we; + logic perf_cnt_sel_2_metric_2_re; + logic [15:0] perf_cnt_sel_3_hart_3_qs; + logic [15:0] perf_cnt_sel_3_hart_3_wd; + logic perf_cnt_sel_3_hart_3_we; + logic perf_cnt_sel_3_hart_3_re; + logic [15:0] perf_cnt_sel_3_metric_3_qs; + logic [15:0] perf_cnt_sel_3_metric_3_wd; + logic perf_cnt_sel_3_metric_3_we; + logic perf_cnt_sel_3_metric_3_re; + logic [15:0] perf_cnt_sel_4_hart_4_qs; + logic [15:0] perf_cnt_sel_4_hart_4_wd; + logic perf_cnt_sel_4_hart_4_we; + logic perf_cnt_sel_4_hart_4_re; + logic [15:0] perf_cnt_sel_4_metric_4_qs; + logic [15:0] perf_cnt_sel_4_metric_4_wd; + logic perf_cnt_sel_4_metric_4_we; + logic perf_cnt_sel_4_metric_4_re; + logic [15:0] perf_cnt_sel_5_hart_5_qs; + logic [15:0] perf_cnt_sel_5_hart_5_wd; + logic perf_cnt_sel_5_hart_5_we; + logic perf_cnt_sel_5_hart_5_re; + logic [15:0] perf_cnt_sel_5_metric_5_qs; + logic [15:0] perf_cnt_sel_5_metric_5_wd; + logic perf_cnt_sel_5_metric_5_we; + logic perf_cnt_sel_5_metric_5_re; + logic [15:0] perf_cnt_sel_6_hart_6_qs; + logic [15:0] perf_cnt_sel_6_hart_6_wd; + logic perf_cnt_sel_6_hart_6_we; + logic perf_cnt_sel_6_hart_6_re; + logic [15:0] perf_cnt_sel_6_metric_6_qs; + logic [15:0] perf_cnt_sel_6_metric_6_wd; + logic perf_cnt_sel_6_metric_6_we; + logic perf_cnt_sel_6_metric_6_re; + logic [15:0] perf_cnt_sel_7_hart_7_qs; + logic [15:0] perf_cnt_sel_7_hart_7_wd; + logic perf_cnt_sel_7_hart_7_we; + logic perf_cnt_sel_7_hart_7_re; + logic [15:0] perf_cnt_sel_7_metric_7_qs; + logic [15:0] perf_cnt_sel_7_metric_7_wd; + logic perf_cnt_sel_7_metric_7_we; + logic perf_cnt_sel_7_metric_7_re; + logic [15:0] perf_cnt_sel_8_hart_8_qs; + logic [15:0] perf_cnt_sel_8_hart_8_wd; + logic perf_cnt_sel_8_hart_8_we; + logic perf_cnt_sel_8_hart_8_re; + logic [15:0] perf_cnt_sel_8_metric_8_qs; + logic [15:0] perf_cnt_sel_8_metric_8_wd; + logic perf_cnt_sel_8_metric_8_we; + logic perf_cnt_sel_8_metric_8_re; + logic [15:0] perf_cnt_sel_9_hart_9_qs; + logic [15:0] perf_cnt_sel_9_hart_9_wd; + logic perf_cnt_sel_9_hart_9_we; + logic perf_cnt_sel_9_hart_9_re; + logic [15:0] perf_cnt_sel_9_metric_9_qs; + logic [15:0] perf_cnt_sel_9_metric_9_wd; + logic perf_cnt_sel_9_metric_9_we; + logic perf_cnt_sel_9_metric_9_re; + logic [15:0] perf_cnt_sel_10_hart_10_qs; + logic [15:0] perf_cnt_sel_10_hart_10_wd; + logic perf_cnt_sel_10_hart_10_we; + logic perf_cnt_sel_10_hart_10_re; + logic [15:0] perf_cnt_sel_10_metric_10_qs; + logic [15:0] perf_cnt_sel_10_metric_10_wd; + logic perf_cnt_sel_10_metric_10_we; + logic perf_cnt_sel_10_metric_10_re; + logic [15:0] perf_cnt_sel_11_hart_11_qs; + logic [15:0] perf_cnt_sel_11_hart_11_wd; + logic perf_cnt_sel_11_hart_11_we; + logic perf_cnt_sel_11_hart_11_re; + logic [15:0] perf_cnt_sel_11_metric_11_qs; + logic [15:0] perf_cnt_sel_11_metric_11_wd; + logic perf_cnt_sel_11_metric_11_we; + logic perf_cnt_sel_11_metric_11_re; + logic [15:0] perf_cnt_sel_12_hart_12_qs; + logic [15:0] perf_cnt_sel_12_hart_12_wd; + logic perf_cnt_sel_12_hart_12_we; + logic perf_cnt_sel_12_hart_12_re; + logic [15:0] perf_cnt_sel_12_metric_12_qs; + logic [15:0] perf_cnt_sel_12_metric_12_wd; + logic perf_cnt_sel_12_metric_12_we; + logic perf_cnt_sel_12_metric_12_re; + logic [15:0] perf_cnt_sel_13_hart_13_qs; + logic [15:0] perf_cnt_sel_13_hart_13_wd; + logic perf_cnt_sel_13_hart_13_we; + logic perf_cnt_sel_13_hart_13_re; + logic [15:0] perf_cnt_sel_13_metric_13_qs; + logic [15:0] perf_cnt_sel_13_metric_13_wd; + logic perf_cnt_sel_13_metric_13_we; + logic perf_cnt_sel_13_metric_13_re; + logic [15:0] perf_cnt_sel_14_hart_14_qs; + logic [15:0] perf_cnt_sel_14_hart_14_wd; + logic perf_cnt_sel_14_hart_14_we; + logic perf_cnt_sel_14_hart_14_re; + logic [15:0] perf_cnt_sel_14_metric_14_qs; + logic [15:0] perf_cnt_sel_14_metric_14_wd; + logic perf_cnt_sel_14_metric_14_we; + logic perf_cnt_sel_14_metric_14_re; + logic [15:0] perf_cnt_sel_15_hart_15_qs; + logic [15:0] perf_cnt_sel_15_hart_15_wd; + logic perf_cnt_sel_15_hart_15_we; + logic perf_cnt_sel_15_hart_15_re; + logic [15:0] perf_cnt_sel_15_metric_15_qs; + logic [15:0] perf_cnt_sel_15_metric_15_wd; + logic perf_cnt_sel_15_metric_15_we; + logic perf_cnt_sel_15_metric_15_re; + logic [47:0] perf_cnt_0_qs; + logic [47:0] perf_cnt_0_wd; + logic perf_cnt_0_we; + logic perf_cnt_0_re; + logic [47:0] perf_cnt_1_qs; + logic [47:0] perf_cnt_1_wd; + logic perf_cnt_1_we; + logic perf_cnt_1_re; + logic [47:0] perf_cnt_2_qs; + logic [47:0] perf_cnt_2_wd; + logic perf_cnt_2_we; + logic perf_cnt_2_re; + logic [47:0] perf_cnt_3_qs; + logic [47:0] perf_cnt_3_wd; + logic perf_cnt_3_we; + logic perf_cnt_3_re; + logic [47:0] perf_cnt_4_qs; + logic [47:0] perf_cnt_4_wd; + logic perf_cnt_4_we; + logic perf_cnt_4_re; + logic [47:0] perf_cnt_5_qs; + logic [47:0] perf_cnt_5_wd; + logic perf_cnt_5_we; + logic perf_cnt_5_re; + logic [47:0] perf_cnt_6_qs; + logic [47:0] perf_cnt_6_wd; + logic perf_cnt_6_we; + logic perf_cnt_6_re; + logic [47:0] perf_cnt_7_qs; + logic [47:0] perf_cnt_7_wd; + logic perf_cnt_7_we; + logic perf_cnt_7_re; + logic [47:0] perf_cnt_8_qs; + logic [47:0] perf_cnt_8_wd; + logic perf_cnt_8_we; + logic perf_cnt_8_re; + logic [47:0] perf_cnt_9_qs; + logic [47:0] perf_cnt_9_wd; + logic perf_cnt_9_we; + logic perf_cnt_9_re; + logic [47:0] perf_cnt_10_qs; + logic [47:0] perf_cnt_10_wd; + logic perf_cnt_10_we; + logic perf_cnt_10_re; + logic [47:0] perf_cnt_11_qs; + logic [47:0] perf_cnt_11_wd; + logic perf_cnt_11_we; + logic perf_cnt_11_re; + logic [47:0] perf_cnt_12_qs; + logic [47:0] perf_cnt_12_wd; + logic perf_cnt_12_we; + logic perf_cnt_12_re; + logic [47:0] perf_cnt_13_qs; + logic [47:0] perf_cnt_13_wd; + logic perf_cnt_13_we; + logic perf_cnt_13_re; + logic [47:0] perf_cnt_14_qs; + logic [47:0] perf_cnt_14_wd; + logic perf_cnt_14_we; + logic perf_cnt_14_re; + logic [47:0] perf_cnt_15_qs; + logic [47:0] perf_cnt_15_wd; + logic perf_cnt_15_we; + logic perf_cnt_15_re; logic [31:0] cl_clint_set_wd; logic cl_clint_set_we; logic [31:0] cl_clint_clear_wd; @@ -303,20 +319,20 @@ module snitch_cluster_peripheral_reg_top #( // Register instances - // Subregister 0 of Multireg perf_counter_enable - // R[perf_counter_enable_0]: V(False) + // Subregister 0 of Multireg perf_cnt_en + // R[perf_cnt_en_0]: V(False) prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_perf_counter_enable_0 ( + ) u_perf_cnt_en_0 ( .clk_i (clk_i), .rst_ni(rst_ni), // from register interface - .we(perf_counter_enable_0_we), - .wd(perf_counter_enable_0_wd), + .we(perf_cnt_en_0_we), + .wd(perf_cnt_en_0_wd), // from internal hardware .de(1'b0), @@ -324,26 +340,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe(), - .q (reg2hw.perf_counter_enable[0].q), + .q (reg2hw.perf_cnt_en[0].q), // to register interface (read) - .qs(perf_counter_enable_0_qs) + .qs(perf_cnt_en_0_qs) ); - // Subregister 1 of Multireg perf_counter_enable - // R[perf_counter_enable_1]: V(False) + // Subregister 1 of Multireg perf_cnt_en + // R[perf_cnt_en_1]: V(False) prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_perf_counter_enable_1 ( + ) u_perf_cnt_en_1 ( .clk_i (clk_i), .rst_ni(rst_ni), // from register interface - .we(perf_counter_enable_1_we), - .wd(perf_counter_enable_1_wd), + .we(perf_cnt_en_1_we), + .wd(perf_cnt_en_1_wd), // from internal hardware .de(1'b0), @@ -351,26 +367,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe(), - .q (reg2hw.perf_counter_enable[1].q), + .q (reg2hw.perf_cnt_en[1].q), // to register interface (read) - .qs(perf_counter_enable_1_qs) + .qs(perf_cnt_en_1_qs) ); - // Subregister 2 of Multireg perf_counter_enable - // R[perf_counter_enable_2]: V(False) + // Subregister 2 of Multireg perf_cnt_en + // R[perf_cnt_en_2]: V(False) prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_perf_counter_enable_2 ( + ) u_perf_cnt_en_2 ( .clk_i (clk_i), .rst_ni(rst_ni), // from register interface - .we(perf_counter_enable_2_we), - .wd(perf_counter_enable_2_wd), + .we(perf_cnt_en_2_we), + .wd(perf_cnt_en_2_wd), // from internal hardware .de(1'b0), @@ -378,26 +394,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe(), - .q (reg2hw.perf_counter_enable[2].q), + .q (reg2hw.perf_cnt_en[2].q), // to register interface (read) - .qs(perf_counter_enable_2_qs) + .qs(perf_cnt_en_2_qs) ); - // Subregister 3 of Multireg perf_counter_enable - // R[perf_counter_enable_3]: V(False) + // Subregister 3 of Multireg perf_cnt_en + // R[perf_cnt_en_3]: V(False) prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_perf_counter_enable_3 ( + ) u_perf_cnt_en_3 ( .clk_i (clk_i), .rst_ni(rst_ni), // from register interface - .we(perf_counter_enable_3_we), - .wd(perf_counter_enable_3_wd), + .we(perf_cnt_en_3_we), + .wd(perf_cnt_en_3_wd), // from internal hardware .de(1'b0), @@ -405,26 +421,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe(), - .q (reg2hw.perf_counter_enable[3].q), + .q (reg2hw.perf_cnt_en[3].q), // to register interface (read) - .qs(perf_counter_enable_3_qs) + .qs(perf_cnt_en_3_qs) ); - // Subregister 4 of Multireg perf_counter_enable - // R[perf_counter_enable_4]: V(False) + // Subregister 4 of Multireg perf_cnt_en + // R[perf_cnt_en_4]: V(False) prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_perf_counter_enable_4 ( + ) u_perf_cnt_en_4 ( .clk_i (clk_i), .rst_ni(rst_ni), // from register interface - .we(perf_counter_enable_4_we), - .wd(perf_counter_enable_4_wd), + .we(perf_cnt_en_4_we), + .wd(perf_cnt_en_4_wd), // from internal hardware .de(1'b0), @@ -432,26 +448,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe(), - .q (reg2hw.perf_counter_enable[4].q), + .q (reg2hw.perf_cnt_en[4].q), // to register interface (read) - .qs(perf_counter_enable_4_qs) + .qs(perf_cnt_en_4_qs) ); - // Subregister 5 of Multireg perf_counter_enable - // R[perf_counter_enable_5]: V(False) + // Subregister 5 of Multireg perf_cnt_en + // R[perf_cnt_en_5]: V(False) prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_perf_counter_enable_5 ( + ) u_perf_cnt_en_5 ( .clk_i (clk_i), .rst_ni(rst_ni), // from register interface - .we(perf_counter_enable_5_we), - .wd(perf_counter_enable_5_wd), + .we(perf_cnt_en_5_we), + .wd(perf_cnt_en_5_wd), // from internal hardware .de(1'b0), @@ -459,26 +475,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe(), - .q (reg2hw.perf_counter_enable[5].q), + .q (reg2hw.perf_cnt_en[5].q), // to register interface (read) - .qs(perf_counter_enable_5_qs) + .qs(perf_cnt_en_5_qs) ); - // Subregister 6 of Multireg perf_counter_enable - // R[perf_counter_enable_6]: V(False) + // Subregister 6 of Multireg perf_cnt_en + // R[perf_cnt_en_6]: V(False) prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_perf_counter_enable_6 ( + ) u_perf_cnt_en_6 ( .clk_i (clk_i), .rst_ni(rst_ni), // from register interface - .we(perf_counter_enable_6_we), - .wd(perf_counter_enable_6_wd), + .we(perf_cnt_en_6_we), + .wd(perf_cnt_en_6_wd), // from internal hardware .de(1'b0), @@ -486,26 +502,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe(), - .q (reg2hw.perf_counter_enable[6].q), + .q (reg2hw.perf_cnt_en[6].q), // to register interface (read) - .qs(perf_counter_enable_6_qs) + .qs(perf_cnt_en_6_qs) ); - // Subregister 7 of Multireg perf_counter_enable - // R[perf_counter_enable_7]: V(False) + // Subregister 7 of Multireg perf_cnt_en + // R[perf_cnt_en_7]: V(False) prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_perf_counter_enable_7 ( + ) u_perf_cnt_en_7 ( .clk_i (clk_i), .rst_ni(rst_ni), // from register interface - .we(perf_counter_enable_7_we), - .wd(perf_counter_enable_7_wd), + .we(perf_cnt_en_7_we), + .wd(perf_cnt_en_7_wd), // from internal hardware .de(1'b0), @@ -513,26 +529,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe(), - .q (reg2hw.perf_counter_enable[7].q), + .q (reg2hw.perf_cnt_en[7].q), // to register interface (read) - .qs(perf_counter_enable_7_qs) + .qs(perf_cnt_en_7_qs) ); - // Subregister 8 of Multireg perf_counter_enable - // R[perf_counter_enable_8]: V(False) + // Subregister 8 of Multireg perf_cnt_en + // R[perf_cnt_en_8]: V(False) prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_perf_counter_enable_8 ( + ) u_perf_cnt_en_8 ( .clk_i (clk_i), .rst_ni(rst_ni), // from register interface - .we(perf_counter_enable_8_we), - .wd(perf_counter_enable_8_wd), + .we(perf_cnt_en_8_we), + .wd(perf_cnt_en_8_wd), // from internal hardware .de(1'b0), @@ -540,26 +556,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe(), - .q (reg2hw.perf_counter_enable[8].q), + .q (reg2hw.perf_cnt_en[8].q), // to register interface (read) - .qs(perf_counter_enable_8_qs) + .qs(perf_cnt_en_8_qs) ); - // Subregister 9 of Multireg perf_counter_enable - // R[perf_counter_enable_9]: V(False) + // Subregister 9 of Multireg perf_cnt_en + // R[perf_cnt_en_9]: V(False) prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_perf_counter_enable_9 ( + ) u_perf_cnt_en_9 ( .clk_i (clk_i), .rst_ni(rst_ni), // from register interface - .we(perf_counter_enable_9_we), - .wd(perf_counter_enable_9_wd), + .we(perf_cnt_en_9_we), + .wd(perf_cnt_en_9_wd), // from internal hardware .de(1'b0), @@ -567,26 +583,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe(), - .q (reg2hw.perf_counter_enable[9].q), + .q (reg2hw.perf_cnt_en[9].q), // to register interface (read) - .qs(perf_counter_enable_9_qs) + .qs(perf_cnt_en_9_qs) ); - // Subregister 10 of Multireg perf_counter_enable - // R[perf_counter_enable_10]: V(False) + // Subregister 10 of Multireg perf_cnt_en + // R[perf_cnt_en_10]: V(False) prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_perf_counter_enable_10 ( + ) u_perf_cnt_en_10 ( .clk_i (clk_i), .rst_ni(rst_ni), // from register interface - .we(perf_counter_enable_10_we), - .wd(perf_counter_enable_10_wd), + .we(perf_cnt_en_10_we), + .wd(perf_cnt_en_10_wd), // from internal hardware .de(1'b0), @@ -594,26 +610,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe(), - .q (reg2hw.perf_counter_enable[10].q), + .q (reg2hw.perf_cnt_en[10].q), // to register interface (read) - .qs(perf_counter_enable_10_qs) + .qs(perf_cnt_en_10_qs) ); - // Subregister 11 of Multireg perf_counter_enable - // R[perf_counter_enable_11]: V(False) + // Subregister 11 of Multireg perf_cnt_en + // R[perf_cnt_en_11]: V(False) prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_perf_counter_enable_11 ( + ) u_perf_cnt_en_11 ( .clk_i (clk_i), .rst_ni(rst_ni), // from register interface - .we(perf_counter_enable_11_we), - .wd(perf_counter_enable_11_wd), + .we(perf_cnt_en_11_we), + .wd(perf_cnt_en_11_wd), // from internal hardware .de(1'b0), @@ -621,26 +637,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe(), - .q (reg2hw.perf_counter_enable[11].q), + .q (reg2hw.perf_cnt_en[11].q), // to register interface (read) - .qs(perf_counter_enable_11_qs) + .qs(perf_cnt_en_11_qs) ); - // Subregister 12 of Multireg perf_counter_enable - // R[perf_counter_enable_12]: V(False) + // Subregister 12 of Multireg perf_cnt_en + // R[perf_cnt_en_12]: V(False) prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_perf_counter_enable_12 ( + ) u_perf_cnt_en_12 ( .clk_i (clk_i), .rst_ni(rst_ni), // from register interface - .we(perf_counter_enable_12_we), - .wd(perf_counter_enable_12_wd), + .we(perf_cnt_en_12_we), + .wd(perf_cnt_en_12_wd), // from internal hardware .de(1'b0), @@ -648,26 +664,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe(), - .q (reg2hw.perf_counter_enable[12].q), + .q (reg2hw.perf_cnt_en[12].q), // to register interface (read) - .qs(perf_counter_enable_12_qs) + .qs(perf_cnt_en_12_qs) ); - // Subregister 13 of Multireg perf_counter_enable - // R[perf_counter_enable_13]: V(False) + // Subregister 13 of Multireg perf_cnt_en + // R[perf_cnt_en_13]: V(False) prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_perf_counter_enable_13 ( + ) u_perf_cnt_en_13 ( .clk_i (clk_i), .rst_ni(rst_ni), // from register interface - .we(perf_counter_enable_13_we), - .wd(perf_counter_enable_13_wd), + .we(perf_cnt_en_13_we), + .wd(perf_cnt_en_13_wd), // from internal hardware .de(1'b0), @@ -675,26 +691,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe(), - .q (reg2hw.perf_counter_enable[13].q), + .q (reg2hw.perf_cnt_en[13].q), // to register interface (read) - .qs(perf_counter_enable_13_qs) + .qs(perf_cnt_en_13_qs) ); - // Subregister 14 of Multireg perf_counter_enable - // R[perf_counter_enable_14]: V(False) + // Subregister 14 of Multireg perf_cnt_en + // R[perf_cnt_en_14]: V(False) prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_perf_counter_enable_14 ( + ) u_perf_cnt_en_14 ( .clk_i (clk_i), .rst_ni(rst_ni), // from register interface - .we(perf_counter_enable_14_we), - .wd(perf_counter_enable_14_wd), + .we(perf_cnt_en_14_we), + .wd(perf_cnt_en_14_wd), // from internal hardware .de(1'b0), @@ -702,26 +718,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe(), - .q (reg2hw.perf_counter_enable[14].q), + .q (reg2hw.perf_cnt_en[14].q), // to register interface (read) - .qs(perf_counter_enable_14_qs) + .qs(perf_cnt_en_14_qs) ); - // Subregister 15 of Multireg perf_counter_enable - // R[perf_counter_enable_15]: V(False) + // Subregister 15 of Multireg perf_cnt_en + // R[perf_cnt_en_15]: V(False) prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_perf_counter_enable_15 ( + ) u_perf_cnt_en_15 ( .clk_i (clk_i), .rst_ni(rst_ni), // from register interface - .we(perf_counter_enable_15_we), - .wd(perf_counter_enable_15_wd), + .we(perf_cnt_en_15_we), + .wd(perf_cnt_en_15_wd), // from internal hardware .de(1'b0), @@ -729,960 +745,798 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe(), - .q (reg2hw.perf_counter_enable[15].q), + .q (reg2hw.perf_cnt_en[15].q), // to register interface (read) - .qs(perf_counter_enable_15_qs) + .qs(perf_cnt_en_15_qs) ); - // Subregister 0 of Multireg perf_counter_select - // R[perf_counter_select_0]: V(True) + // Subregister 0 of Multireg perf_cnt_sel + // R[perf_cnt_sel_0]: V(True) + // F[hart_0]: 15:0 prim_subreg_ext #( - .DW(10) - ) u_perf_counter_select_0 ( - .re (perf_counter_select_0_re), - .we (perf_counter_select_0_we), - .wd (perf_counter_select_0_wd), - .d (hw2reg.perf_counter_select[0].d), + .DW(16) + ) u_perf_cnt_sel_0_hart_0 ( + .re (perf_cnt_sel_0_hart_0_re), + .we (perf_cnt_sel_0_hart_0_we), + .wd (perf_cnt_sel_0_hart_0_wd), + .d (hw2reg.perf_cnt_sel[0].hart.d), .qre(), - .qe (reg2hw.perf_counter_select[0].qe), - .q (reg2hw.perf_counter_select[0].q), - .qs (perf_counter_select_0_qs) + .qe (reg2hw.perf_cnt_sel[0].hart.qe), + .q (reg2hw.perf_cnt_sel[0].hart.q), + .qs (perf_cnt_sel_0_hart_0_qs) ); - // Subregister 1 of Multireg perf_counter_select - // R[perf_counter_select_1]: V(True) + // F[metric_0]: 31:16 prim_subreg_ext #( - .DW(10) - ) u_perf_counter_select_1 ( - .re (perf_counter_select_1_re), - .we (perf_counter_select_1_we), - .wd (perf_counter_select_1_wd), - .d (hw2reg.perf_counter_select[1].d), + .DW(16) + ) u_perf_cnt_sel_0_metric_0 ( + .re (perf_cnt_sel_0_metric_0_re), + .we (perf_cnt_sel_0_metric_0_we), + .wd (perf_cnt_sel_0_metric_0_wd), + .d (hw2reg.perf_cnt_sel[0].metric.d), .qre(), - .qe (reg2hw.perf_counter_select[1].qe), - .q (reg2hw.perf_counter_select[1].q), - .qs (perf_counter_select_1_qs) + .qe (reg2hw.perf_cnt_sel[0].metric.qe), + .q (reg2hw.perf_cnt_sel[0].metric.q), + .qs (perf_cnt_sel_0_metric_0_qs) ); - // Subregister 2 of Multireg perf_counter_select - // R[perf_counter_select_2]: V(True) + // Subregister 1 of Multireg perf_cnt_sel + // R[perf_cnt_sel_1]: V(True) + + // F[hart_1]: 15:0 prim_subreg_ext #( - .DW(10) - ) u_perf_counter_select_2 ( - .re (perf_counter_select_2_re), - .we (perf_counter_select_2_we), - .wd (perf_counter_select_2_wd), - .d (hw2reg.perf_counter_select[2].d), + .DW(16) + ) u_perf_cnt_sel_1_hart_1 ( + .re (perf_cnt_sel_1_hart_1_re), + .we (perf_cnt_sel_1_hart_1_we), + .wd (perf_cnt_sel_1_hart_1_wd), + .d (hw2reg.perf_cnt_sel[1].hart.d), .qre(), - .qe (reg2hw.perf_counter_select[2].qe), - .q (reg2hw.perf_counter_select[2].q), - .qs (perf_counter_select_2_qs) + .qe (reg2hw.perf_cnt_sel[1].hart.qe), + .q (reg2hw.perf_cnt_sel[1].hart.q), + .qs (perf_cnt_sel_1_hart_1_qs) ); - // Subregister 3 of Multireg perf_counter_select - // R[perf_counter_select_3]: V(True) + // F[metric_1]: 31:16 prim_subreg_ext #( - .DW(10) - ) u_perf_counter_select_3 ( - .re (perf_counter_select_3_re), - .we (perf_counter_select_3_we), - .wd (perf_counter_select_3_wd), - .d (hw2reg.perf_counter_select[3].d), + .DW(16) + ) u_perf_cnt_sel_1_metric_1 ( + .re (perf_cnt_sel_1_metric_1_re), + .we (perf_cnt_sel_1_metric_1_we), + .wd (perf_cnt_sel_1_metric_1_wd), + .d (hw2reg.perf_cnt_sel[1].metric.d), .qre(), - .qe (reg2hw.perf_counter_select[3].qe), - .q (reg2hw.perf_counter_select[3].q), - .qs (perf_counter_select_3_qs) + .qe (reg2hw.perf_cnt_sel[1].metric.qe), + .q (reg2hw.perf_cnt_sel[1].metric.q), + .qs (perf_cnt_sel_1_metric_1_qs) ); - // Subregister 4 of Multireg perf_counter_select - // R[perf_counter_select_4]: V(True) + // Subregister 2 of Multireg perf_cnt_sel + // R[perf_cnt_sel_2]: V(True) + + // F[hart_2]: 15:0 prim_subreg_ext #( - .DW(10) - ) u_perf_counter_select_4 ( - .re (perf_counter_select_4_re), - .we (perf_counter_select_4_we), - .wd (perf_counter_select_4_wd), - .d (hw2reg.perf_counter_select[4].d), + .DW(16) + ) u_perf_cnt_sel_2_hart_2 ( + .re (perf_cnt_sel_2_hart_2_re), + .we (perf_cnt_sel_2_hart_2_we), + .wd (perf_cnt_sel_2_hart_2_wd), + .d (hw2reg.perf_cnt_sel[2].hart.d), .qre(), - .qe (reg2hw.perf_counter_select[4].qe), - .q (reg2hw.perf_counter_select[4].q), - .qs (perf_counter_select_4_qs) + .qe (reg2hw.perf_cnt_sel[2].hart.qe), + .q (reg2hw.perf_cnt_sel[2].hart.q), + .qs (perf_cnt_sel_2_hart_2_qs) ); - // Subregister 5 of Multireg perf_counter_select - // R[perf_counter_select_5]: V(True) + // F[metric_2]: 31:16 prim_subreg_ext #( - .DW(10) - ) u_perf_counter_select_5 ( - .re (perf_counter_select_5_re), - .we (perf_counter_select_5_we), - .wd (perf_counter_select_5_wd), - .d (hw2reg.perf_counter_select[5].d), + .DW(16) + ) u_perf_cnt_sel_2_metric_2 ( + .re (perf_cnt_sel_2_metric_2_re), + .we (perf_cnt_sel_2_metric_2_we), + .wd (perf_cnt_sel_2_metric_2_wd), + .d (hw2reg.perf_cnt_sel[2].metric.d), .qre(), - .qe (reg2hw.perf_counter_select[5].qe), - .q (reg2hw.perf_counter_select[5].q), - .qs (perf_counter_select_5_qs) + .qe (reg2hw.perf_cnt_sel[2].metric.qe), + .q (reg2hw.perf_cnt_sel[2].metric.q), + .qs (perf_cnt_sel_2_metric_2_qs) ); - // Subregister 6 of Multireg perf_counter_select - // R[perf_counter_select_6]: V(True) + // Subregister 3 of Multireg perf_cnt_sel + // R[perf_cnt_sel_3]: V(True) + + // F[hart_3]: 15:0 prim_subreg_ext #( - .DW(10) - ) u_perf_counter_select_6 ( - .re (perf_counter_select_6_re), - .we (perf_counter_select_6_we), - .wd (perf_counter_select_6_wd), - .d (hw2reg.perf_counter_select[6].d), + .DW(16) + ) u_perf_cnt_sel_3_hart_3 ( + .re (perf_cnt_sel_3_hart_3_re), + .we (perf_cnt_sel_3_hart_3_we), + .wd (perf_cnt_sel_3_hart_3_wd), + .d (hw2reg.perf_cnt_sel[3].hart.d), .qre(), - .qe (reg2hw.perf_counter_select[6].qe), - .q (reg2hw.perf_counter_select[6].q), - .qs (perf_counter_select_6_qs) + .qe (reg2hw.perf_cnt_sel[3].hart.qe), + .q (reg2hw.perf_cnt_sel[3].hart.q), + .qs (perf_cnt_sel_3_hart_3_qs) ); - // Subregister 7 of Multireg perf_counter_select - // R[perf_counter_select_7]: V(True) + // F[metric_3]: 31:16 prim_subreg_ext #( - .DW(10) - ) u_perf_counter_select_7 ( - .re (perf_counter_select_7_re), - .we (perf_counter_select_7_we), - .wd (perf_counter_select_7_wd), - .d (hw2reg.perf_counter_select[7].d), + .DW(16) + ) u_perf_cnt_sel_3_metric_3 ( + .re (perf_cnt_sel_3_metric_3_re), + .we (perf_cnt_sel_3_metric_3_we), + .wd (perf_cnt_sel_3_metric_3_wd), + .d (hw2reg.perf_cnt_sel[3].metric.d), .qre(), - .qe (reg2hw.perf_counter_select[7].qe), - .q (reg2hw.perf_counter_select[7].q), - .qs (perf_counter_select_7_qs) + .qe (reg2hw.perf_cnt_sel[3].metric.qe), + .q (reg2hw.perf_cnt_sel[3].metric.q), + .qs (perf_cnt_sel_3_metric_3_qs) ); - // Subregister 8 of Multireg perf_counter_select - // R[perf_counter_select_8]: V(True) + // Subregister 4 of Multireg perf_cnt_sel + // R[perf_cnt_sel_4]: V(True) + + // F[hart_4]: 15:0 prim_subreg_ext #( - .DW(10) - ) u_perf_counter_select_8 ( - .re (perf_counter_select_8_re), - .we (perf_counter_select_8_we), - .wd (perf_counter_select_8_wd), - .d (hw2reg.perf_counter_select[8].d), + .DW(16) + ) u_perf_cnt_sel_4_hart_4 ( + .re (perf_cnt_sel_4_hart_4_re), + .we (perf_cnt_sel_4_hart_4_we), + .wd (perf_cnt_sel_4_hart_4_wd), + .d (hw2reg.perf_cnt_sel[4].hart.d), .qre(), - .qe (reg2hw.perf_counter_select[8].qe), - .q (reg2hw.perf_counter_select[8].q), - .qs (perf_counter_select_8_qs) + .qe (reg2hw.perf_cnt_sel[4].hart.qe), + .q (reg2hw.perf_cnt_sel[4].hart.q), + .qs (perf_cnt_sel_4_hart_4_qs) ); - // Subregister 9 of Multireg perf_counter_select - // R[perf_counter_select_9]: V(True) + // F[metric_4]: 31:16 prim_subreg_ext #( - .DW(10) - ) u_perf_counter_select_9 ( - .re (perf_counter_select_9_re), - .we (perf_counter_select_9_we), - .wd (perf_counter_select_9_wd), - .d (hw2reg.perf_counter_select[9].d), + .DW(16) + ) u_perf_cnt_sel_4_metric_4 ( + .re (perf_cnt_sel_4_metric_4_re), + .we (perf_cnt_sel_4_metric_4_we), + .wd (perf_cnt_sel_4_metric_4_wd), + .d (hw2reg.perf_cnt_sel[4].metric.d), .qre(), - .qe (reg2hw.perf_counter_select[9].qe), - .q (reg2hw.perf_counter_select[9].q), - .qs (perf_counter_select_9_qs) + .qe (reg2hw.perf_cnt_sel[4].metric.qe), + .q (reg2hw.perf_cnt_sel[4].metric.q), + .qs (perf_cnt_sel_4_metric_4_qs) ); - // Subregister 10 of Multireg perf_counter_select - // R[perf_counter_select_10]: V(True) + // Subregister 5 of Multireg perf_cnt_sel + // R[perf_cnt_sel_5]: V(True) + + // F[hart_5]: 15:0 prim_subreg_ext #( - .DW(10) - ) u_perf_counter_select_10 ( - .re (perf_counter_select_10_re), - .we (perf_counter_select_10_we), - .wd (perf_counter_select_10_wd), - .d (hw2reg.perf_counter_select[10].d), + .DW(16) + ) u_perf_cnt_sel_5_hart_5 ( + .re (perf_cnt_sel_5_hart_5_re), + .we (perf_cnt_sel_5_hart_5_we), + .wd (perf_cnt_sel_5_hart_5_wd), + .d (hw2reg.perf_cnt_sel[5].hart.d), .qre(), - .qe (reg2hw.perf_counter_select[10].qe), - .q (reg2hw.perf_counter_select[10].q), - .qs (perf_counter_select_10_qs) + .qe (reg2hw.perf_cnt_sel[5].hart.qe), + .q (reg2hw.perf_cnt_sel[5].hart.q), + .qs (perf_cnt_sel_5_hart_5_qs) ); - // Subregister 11 of Multireg perf_counter_select - // R[perf_counter_select_11]: V(True) + // F[metric_5]: 31:16 prim_subreg_ext #( - .DW(10) - ) u_perf_counter_select_11 ( - .re (perf_counter_select_11_re), - .we (perf_counter_select_11_we), - .wd (perf_counter_select_11_wd), - .d (hw2reg.perf_counter_select[11].d), + .DW(16) + ) u_perf_cnt_sel_5_metric_5 ( + .re (perf_cnt_sel_5_metric_5_re), + .we (perf_cnt_sel_5_metric_5_we), + .wd (perf_cnt_sel_5_metric_5_wd), + .d (hw2reg.perf_cnt_sel[5].metric.d), .qre(), - .qe (reg2hw.perf_counter_select[11].qe), - .q (reg2hw.perf_counter_select[11].q), - .qs (perf_counter_select_11_qs) + .qe (reg2hw.perf_cnt_sel[5].metric.qe), + .q (reg2hw.perf_cnt_sel[5].metric.q), + .qs (perf_cnt_sel_5_metric_5_qs) ); - // Subregister 12 of Multireg perf_counter_select - // R[perf_counter_select_12]: V(True) + // Subregister 6 of Multireg perf_cnt_sel + // R[perf_cnt_sel_6]: V(True) + + // F[hart_6]: 15:0 prim_subreg_ext #( - .DW(10) - ) u_perf_counter_select_12 ( - .re (perf_counter_select_12_re), - .we (perf_counter_select_12_we), - .wd (perf_counter_select_12_wd), - .d (hw2reg.perf_counter_select[12].d), + .DW(16) + ) u_perf_cnt_sel_6_hart_6 ( + .re (perf_cnt_sel_6_hart_6_re), + .we (perf_cnt_sel_6_hart_6_we), + .wd (perf_cnt_sel_6_hart_6_wd), + .d (hw2reg.perf_cnt_sel[6].hart.d), .qre(), - .qe (reg2hw.perf_counter_select[12].qe), - .q (reg2hw.perf_counter_select[12].q), - .qs (perf_counter_select_12_qs) + .qe (reg2hw.perf_cnt_sel[6].hart.qe), + .q (reg2hw.perf_cnt_sel[6].hart.q), + .qs (perf_cnt_sel_6_hart_6_qs) ); - // Subregister 13 of Multireg perf_counter_select - // R[perf_counter_select_13]: V(True) + // F[metric_6]: 31:16 prim_subreg_ext #( - .DW(10) - ) u_perf_counter_select_13 ( - .re (perf_counter_select_13_re), - .we (perf_counter_select_13_we), - .wd (perf_counter_select_13_wd), - .d (hw2reg.perf_counter_select[13].d), + .DW(16) + ) u_perf_cnt_sel_6_metric_6 ( + .re (perf_cnt_sel_6_metric_6_re), + .we (perf_cnt_sel_6_metric_6_we), + .wd (perf_cnt_sel_6_metric_6_wd), + .d (hw2reg.perf_cnt_sel[6].metric.d), .qre(), - .qe (reg2hw.perf_counter_select[13].qe), - .q (reg2hw.perf_counter_select[13].q), - .qs (perf_counter_select_13_qs) + .qe (reg2hw.perf_cnt_sel[6].metric.qe), + .q (reg2hw.perf_cnt_sel[6].metric.q), + .qs (perf_cnt_sel_6_metric_6_qs) ); - // Subregister 14 of Multireg perf_counter_select - // R[perf_counter_select_14]: V(True) + // Subregister 7 of Multireg perf_cnt_sel + // R[perf_cnt_sel_7]: V(True) + + // F[hart_7]: 15:0 prim_subreg_ext #( - .DW(10) - ) u_perf_counter_select_14 ( - .re (perf_counter_select_14_re), - .we (perf_counter_select_14_we), - .wd (perf_counter_select_14_wd), - .d (hw2reg.perf_counter_select[14].d), + .DW(16) + ) u_perf_cnt_sel_7_hart_7 ( + .re (perf_cnt_sel_7_hart_7_re), + .we (perf_cnt_sel_7_hart_7_we), + .wd (perf_cnt_sel_7_hart_7_wd), + .d (hw2reg.perf_cnt_sel[7].hart.d), .qre(), - .qe (reg2hw.perf_counter_select[14].qe), - .q (reg2hw.perf_counter_select[14].q), - .qs (perf_counter_select_14_qs) + .qe (reg2hw.perf_cnt_sel[7].hart.qe), + .q (reg2hw.perf_cnt_sel[7].hart.q), + .qs (perf_cnt_sel_7_hart_7_qs) ); - // Subregister 15 of Multireg perf_counter_select - // R[perf_counter_select_15]: V(True) + // F[metric_7]: 31:16 prim_subreg_ext #( - .DW(10) - ) u_perf_counter_select_15 ( - .re (perf_counter_select_15_re), - .we (perf_counter_select_15_we), - .wd (perf_counter_select_15_wd), - .d (hw2reg.perf_counter_select[15].d), + .DW(16) + ) u_perf_cnt_sel_7_metric_7 ( + .re (perf_cnt_sel_7_metric_7_re), + .we (perf_cnt_sel_7_metric_7_we), + .wd (perf_cnt_sel_7_metric_7_wd), + .d (hw2reg.perf_cnt_sel[7].metric.d), .qre(), - .qe (reg2hw.perf_counter_select[15].qe), - .q (reg2hw.perf_counter_select[15].q), - .qs (perf_counter_select_15_qs) + .qe (reg2hw.perf_cnt_sel[7].metric.qe), + .q (reg2hw.perf_cnt_sel[7].metric.q), + .qs (perf_cnt_sel_7_metric_7_qs) ); + // Subregister 8 of Multireg perf_cnt_sel + // R[perf_cnt_sel_8]: V(True) - // Subregister 0 of Multireg perf_counter_hart_select - // R[perf_counter_hart_select_0]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_perf_counter_hart_select_0 ( - .clk_i (clk_i), - .rst_ni(rst_ni), - - // from register interface - .we(perf_counter_hart_select_0_we), - .wd(perf_counter_hart_select_0_wd), - - // from internal hardware - .de(1'b0), - .d ('0), - - // to internal hardware - .qe(), - .q (reg2hw.perf_counter_hart_select[0].q), - - // to register interface (read) - .qs(perf_counter_hart_select_0_qs) + // F[hart_8]: 15:0 + prim_subreg_ext #( + .DW(16) + ) u_perf_cnt_sel_8_hart_8 ( + .re (perf_cnt_sel_8_hart_8_re), + .we (perf_cnt_sel_8_hart_8_we), + .wd (perf_cnt_sel_8_hart_8_wd), + .d (hw2reg.perf_cnt_sel[8].hart.d), + .qre(), + .qe (reg2hw.perf_cnt_sel[8].hart.qe), + .q (reg2hw.perf_cnt_sel[8].hart.q), + .qs (perf_cnt_sel_8_hart_8_qs) ); - // Subregister 1 of Multireg perf_counter_hart_select - // R[perf_counter_hart_select_1]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_perf_counter_hart_select_1 ( - .clk_i (clk_i), - .rst_ni(rst_ni), - - // from register interface - .we(perf_counter_hart_select_1_we), - .wd(perf_counter_hart_select_1_wd), - - // from internal hardware - .de(1'b0), - .d ('0), - - // to internal hardware - .qe(), - .q (reg2hw.perf_counter_hart_select[1].q), - // to register interface (read) - .qs(perf_counter_hart_select_1_qs) + // F[metric_8]: 31:16 + prim_subreg_ext #( + .DW(16) + ) u_perf_cnt_sel_8_metric_8 ( + .re (perf_cnt_sel_8_metric_8_re), + .we (perf_cnt_sel_8_metric_8_we), + .wd (perf_cnt_sel_8_metric_8_wd), + .d (hw2reg.perf_cnt_sel[8].metric.d), + .qre(), + .qe (reg2hw.perf_cnt_sel[8].metric.qe), + .q (reg2hw.perf_cnt_sel[8].metric.q), + .qs (perf_cnt_sel_8_metric_8_qs) ); - // Subregister 2 of Multireg perf_counter_hart_select - // R[perf_counter_hart_select_2]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_perf_counter_hart_select_2 ( - .clk_i (clk_i), - .rst_ni(rst_ni), - - // from register interface - .we(perf_counter_hart_select_2_we), - .wd(perf_counter_hart_select_2_wd), - - // from internal hardware - .de(1'b0), - .d ('0), - // to internal hardware - .qe(), - .q (reg2hw.perf_counter_hart_select[2].q), + // Subregister 9 of Multireg perf_cnt_sel + // R[perf_cnt_sel_9]: V(True) - // to register interface (read) - .qs(perf_counter_hart_select_2_qs) + // F[hart_9]: 15:0 + prim_subreg_ext #( + .DW(16) + ) u_perf_cnt_sel_9_hart_9 ( + .re (perf_cnt_sel_9_hart_9_re), + .we (perf_cnt_sel_9_hart_9_we), + .wd (perf_cnt_sel_9_hart_9_wd), + .d (hw2reg.perf_cnt_sel[9].hart.d), + .qre(), + .qe (reg2hw.perf_cnt_sel[9].hart.qe), + .q (reg2hw.perf_cnt_sel[9].hart.q), + .qs (perf_cnt_sel_9_hart_9_qs) ); - // Subregister 3 of Multireg perf_counter_hart_select - // R[perf_counter_hart_select_3]: V(False) - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_perf_counter_hart_select_3 ( - .clk_i (clk_i), - .rst_ni(rst_ni), - - // from register interface - .we(perf_counter_hart_select_3_we), - .wd(perf_counter_hart_select_3_wd), - - // from internal hardware - .de(1'b0), - .d ('0), - - // to internal hardware - .qe(), - .q (reg2hw.perf_counter_hart_select[3].q), - - // to register interface (read) - .qs(perf_counter_hart_select_3_qs) + // F[metric_9]: 31:16 + prim_subreg_ext #( + .DW(16) + ) u_perf_cnt_sel_9_metric_9 ( + .re (perf_cnt_sel_9_metric_9_re), + .we (perf_cnt_sel_9_metric_9_we), + .wd (perf_cnt_sel_9_metric_9_wd), + .d (hw2reg.perf_cnt_sel[9].metric.d), + .qre(), + .qe (reg2hw.perf_cnt_sel[9].metric.qe), + .q (reg2hw.perf_cnt_sel[9].metric.q), + .qs (perf_cnt_sel_9_metric_9_qs) ); - // Subregister 4 of Multireg perf_counter_hart_select - // R[perf_counter_hart_select_4]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_perf_counter_hart_select_4 ( - .clk_i (clk_i), - .rst_ni(rst_ni), - - // from register interface - .we(perf_counter_hart_select_4_we), - .wd(perf_counter_hart_select_4_wd), - - // from internal hardware - .de(1'b0), - .d ('0), - // to internal hardware - .qe(), - .q (reg2hw.perf_counter_hart_select[4].q), + // Subregister 10 of Multireg perf_cnt_sel + // R[perf_cnt_sel_10]: V(True) - // to register interface (read) - .qs(perf_counter_hart_select_4_qs) + // F[hart_10]: 15:0 + prim_subreg_ext #( + .DW(16) + ) u_perf_cnt_sel_10_hart_10 ( + .re (perf_cnt_sel_10_hart_10_re), + .we (perf_cnt_sel_10_hart_10_we), + .wd (perf_cnt_sel_10_hart_10_wd), + .d (hw2reg.perf_cnt_sel[10].hart.d), + .qre(), + .qe (reg2hw.perf_cnt_sel[10].hart.qe), + .q (reg2hw.perf_cnt_sel[10].hart.q), + .qs (perf_cnt_sel_10_hart_10_qs) ); - // Subregister 5 of Multireg perf_counter_hart_select - // R[perf_counter_hart_select_5]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_perf_counter_hart_select_5 ( - .clk_i (clk_i), - .rst_ni(rst_ni), - - // from register interface - .we(perf_counter_hart_select_5_we), - .wd(perf_counter_hart_select_5_wd), - // from internal hardware - .de(1'b0), - .d ('0), - - // to internal hardware - .qe(), - .q (reg2hw.perf_counter_hart_select[5].q), - - // to register interface (read) - .qs(perf_counter_hart_select_5_qs) + // F[metric_10]: 31:16 + prim_subreg_ext #( + .DW(16) + ) u_perf_cnt_sel_10_metric_10 ( + .re (perf_cnt_sel_10_metric_10_re), + .we (perf_cnt_sel_10_metric_10_we), + .wd (perf_cnt_sel_10_metric_10_wd), + .d (hw2reg.perf_cnt_sel[10].metric.d), + .qre(), + .qe (reg2hw.perf_cnt_sel[10].metric.qe), + .q (reg2hw.perf_cnt_sel[10].metric.q), + .qs (perf_cnt_sel_10_metric_10_qs) ); - // Subregister 6 of Multireg perf_counter_hart_select - // R[perf_counter_hart_select_6]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_perf_counter_hart_select_6 ( - .clk_i (clk_i), - .rst_ni(rst_ni), - - // from register interface - .we(perf_counter_hart_select_6_we), - .wd(perf_counter_hart_select_6_wd), - - // from internal hardware - .de(1'b0), - .d ('0), - // to internal hardware - .qe(), - .q (reg2hw.perf_counter_hart_select[6].q), + // Subregister 11 of Multireg perf_cnt_sel + // R[perf_cnt_sel_11]: V(True) - // to register interface (read) - .qs(perf_counter_hart_select_6_qs) + // F[hart_11]: 15:0 + prim_subreg_ext #( + .DW(16) + ) u_perf_cnt_sel_11_hart_11 ( + .re (perf_cnt_sel_11_hart_11_re), + .we (perf_cnt_sel_11_hart_11_we), + .wd (perf_cnt_sel_11_hart_11_wd), + .d (hw2reg.perf_cnt_sel[11].hart.d), + .qre(), + .qe (reg2hw.perf_cnt_sel[11].hart.qe), + .q (reg2hw.perf_cnt_sel[11].hart.q), + .qs (perf_cnt_sel_11_hart_11_qs) ); - // Subregister 7 of Multireg perf_counter_hart_select - // R[perf_counter_hart_select_7]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_perf_counter_hart_select_7 ( - .clk_i (clk_i), - .rst_ni(rst_ni), - - // from register interface - .we(perf_counter_hart_select_7_we), - .wd(perf_counter_hart_select_7_wd), - - // from internal hardware - .de(1'b0), - .d ('0), - // to internal hardware - .qe(), - .q (reg2hw.perf_counter_hart_select[7].q), - - // to register interface (read) - .qs(perf_counter_hart_select_7_qs) + // F[metric_11]: 31:16 + prim_subreg_ext #( + .DW(16) + ) u_perf_cnt_sel_11_metric_11 ( + .re (perf_cnt_sel_11_metric_11_re), + .we (perf_cnt_sel_11_metric_11_we), + .wd (perf_cnt_sel_11_metric_11_wd), + .d (hw2reg.perf_cnt_sel[11].metric.d), + .qre(), + .qe (reg2hw.perf_cnt_sel[11].metric.qe), + .q (reg2hw.perf_cnt_sel[11].metric.q), + .qs (perf_cnt_sel_11_metric_11_qs) ); - // Subregister 8 of Multireg perf_counter_hart_select - // R[perf_counter_hart_select_8]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_perf_counter_hart_select_8 ( - .clk_i (clk_i), - .rst_ni(rst_ni), - // from register interface - .we(perf_counter_hart_select_8_we), - .wd(perf_counter_hart_select_8_wd), + // Subregister 12 of Multireg perf_cnt_sel + // R[perf_cnt_sel_12]: V(True) - // from internal hardware - .de(1'b0), - .d ('0), - - // to internal hardware - .qe(), - .q (reg2hw.perf_counter_hart_select[8].q), - - // to register interface (read) - .qs(perf_counter_hart_select_8_qs) + // F[hart_12]: 15:0 + prim_subreg_ext #( + .DW(16) + ) u_perf_cnt_sel_12_hart_12 ( + .re (perf_cnt_sel_12_hart_12_re), + .we (perf_cnt_sel_12_hart_12_we), + .wd (perf_cnt_sel_12_hart_12_wd), + .d (hw2reg.perf_cnt_sel[12].hart.d), + .qre(), + .qe (reg2hw.perf_cnt_sel[12].hart.qe), + .q (reg2hw.perf_cnt_sel[12].hart.q), + .qs (perf_cnt_sel_12_hart_12_qs) ); - // Subregister 9 of Multireg perf_counter_hart_select - // R[perf_counter_hart_select_9]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_perf_counter_hart_select_9 ( - .clk_i (clk_i), - .rst_ni(rst_ni), - - // from register interface - .we(perf_counter_hart_select_9_we), - .wd(perf_counter_hart_select_9_wd), - - // from internal hardware - .de(1'b0), - .d ('0), - - // to internal hardware - .qe(), - .q (reg2hw.perf_counter_hart_select[9].q), - // to register interface (read) - .qs(perf_counter_hart_select_9_qs) + // F[metric_12]: 31:16 + prim_subreg_ext #( + .DW(16) + ) u_perf_cnt_sel_12_metric_12 ( + .re (perf_cnt_sel_12_metric_12_re), + .we (perf_cnt_sel_12_metric_12_we), + .wd (perf_cnt_sel_12_metric_12_wd), + .d (hw2reg.perf_cnt_sel[12].metric.d), + .qre(), + .qe (reg2hw.perf_cnt_sel[12].metric.qe), + .q (reg2hw.perf_cnt_sel[12].metric.q), + .qs (perf_cnt_sel_12_metric_12_qs) ); - // Subregister 10 of Multireg perf_counter_hart_select - // R[perf_counter_hart_select_10]: V(False) - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_perf_counter_hart_select_10 ( - .clk_i (clk_i), - .rst_ni(rst_ni), - - // from register interface - .we(perf_counter_hart_select_10_we), - .wd(perf_counter_hart_select_10_wd), - - // from internal hardware - .de(1'b0), - .d ('0), + // Subregister 13 of Multireg perf_cnt_sel + // R[perf_cnt_sel_13]: V(True) - // to internal hardware - .qe(), - .q (reg2hw.perf_counter_hart_select[10].q), - - // to register interface (read) - .qs(perf_counter_hart_select_10_qs) + // F[hart_13]: 15:0 + prim_subreg_ext #( + .DW(16) + ) u_perf_cnt_sel_13_hart_13 ( + .re (perf_cnt_sel_13_hart_13_re), + .we (perf_cnt_sel_13_hart_13_we), + .wd (perf_cnt_sel_13_hart_13_wd), + .d (hw2reg.perf_cnt_sel[13].hart.d), + .qre(), + .qe (reg2hw.perf_cnt_sel[13].hart.qe), + .q (reg2hw.perf_cnt_sel[13].hart.q), + .qs (perf_cnt_sel_13_hart_13_qs) ); - // Subregister 11 of Multireg perf_counter_hart_select - // R[perf_counter_hart_select_11]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_perf_counter_hart_select_11 ( - .clk_i (clk_i), - .rst_ni(rst_ni), - - // from register interface - .we(perf_counter_hart_select_11_we), - .wd(perf_counter_hart_select_11_wd), - - // from internal hardware - .de(1'b0), - .d ('0), - - // to internal hardware - .qe(), - .q (reg2hw.perf_counter_hart_select[11].q), - // to register interface (read) - .qs(perf_counter_hart_select_11_qs) + // F[metric_13]: 31:16 + prim_subreg_ext #( + .DW(16) + ) u_perf_cnt_sel_13_metric_13 ( + .re (perf_cnt_sel_13_metric_13_re), + .we (perf_cnt_sel_13_metric_13_we), + .wd (perf_cnt_sel_13_metric_13_wd), + .d (hw2reg.perf_cnt_sel[13].metric.d), + .qre(), + .qe (reg2hw.perf_cnt_sel[13].metric.qe), + .q (reg2hw.perf_cnt_sel[13].metric.q), + .qs (perf_cnt_sel_13_metric_13_qs) ); - // Subregister 12 of Multireg perf_counter_hart_select - // R[perf_counter_hart_select_12]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_perf_counter_hart_select_12 ( - .clk_i (clk_i), - .rst_ni(rst_ni), - // from register interface - .we(perf_counter_hart_select_12_we), - .wd(perf_counter_hart_select_12_wd), + // Subregister 14 of Multireg perf_cnt_sel + // R[perf_cnt_sel_14]: V(True) - // from internal hardware - .de(1'b0), - .d ('0), - - // to internal hardware - .qe(), - .q (reg2hw.perf_counter_hart_select[12].q), - - // to register interface (read) - .qs(perf_counter_hart_select_12_qs) + // F[hart_14]: 15:0 + prim_subreg_ext #( + .DW(16) + ) u_perf_cnt_sel_14_hart_14 ( + .re (perf_cnt_sel_14_hart_14_re), + .we (perf_cnt_sel_14_hart_14_we), + .wd (perf_cnt_sel_14_hart_14_wd), + .d (hw2reg.perf_cnt_sel[14].hart.d), + .qre(), + .qe (reg2hw.perf_cnt_sel[14].hart.qe), + .q (reg2hw.perf_cnt_sel[14].hart.q), + .qs (perf_cnt_sel_14_hart_14_qs) ); - // Subregister 13 of Multireg perf_counter_hart_select - // R[perf_counter_hart_select_13]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_perf_counter_hart_select_13 ( - .clk_i (clk_i), - .rst_ni(rst_ni), - - // from register interface - .we(perf_counter_hart_select_13_we), - .wd(perf_counter_hart_select_13_wd), - - // from internal hardware - .de(1'b0), - .d ('0), - - // to internal hardware - .qe(), - .q (reg2hw.perf_counter_hart_select[13].q), - // to register interface (read) - .qs(perf_counter_hart_select_13_qs) + // F[metric_14]: 31:16 + prim_subreg_ext #( + .DW(16) + ) u_perf_cnt_sel_14_metric_14 ( + .re (perf_cnt_sel_14_metric_14_re), + .we (perf_cnt_sel_14_metric_14_we), + .wd (perf_cnt_sel_14_metric_14_wd), + .d (hw2reg.perf_cnt_sel[14].metric.d), + .qre(), + .qe (reg2hw.perf_cnt_sel[14].metric.qe), + .q (reg2hw.perf_cnt_sel[14].metric.q), + .qs (perf_cnt_sel_14_metric_14_qs) ); - // Subregister 14 of Multireg perf_counter_hart_select - // R[perf_counter_hart_select_14]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_perf_counter_hart_select_14 ( - .clk_i (clk_i), - .rst_ni(rst_ni), - - // from register interface - .we(perf_counter_hart_select_14_we), - .wd(perf_counter_hart_select_14_wd), - - // from internal hardware - .de(1'b0), - .d ('0), - // to internal hardware - .qe(), - .q (reg2hw.perf_counter_hart_select[14].q), + // Subregister 15 of Multireg perf_cnt_sel + // R[perf_cnt_sel_15]: V(True) - // to register interface (read) - .qs(perf_counter_hart_select_14_qs) + // F[hart_15]: 15:0 + prim_subreg_ext #( + .DW(16) + ) u_perf_cnt_sel_15_hart_15 ( + .re (perf_cnt_sel_15_hart_15_re), + .we (perf_cnt_sel_15_hart_15_we), + .wd (perf_cnt_sel_15_hart_15_wd), + .d (hw2reg.perf_cnt_sel[15].hart.d), + .qre(), + .qe (reg2hw.perf_cnt_sel[15].hart.qe), + .q (reg2hw.perf_cnt_sel[15].hart.q), + .qs (perf_cnt_sel_15_hart_15_qs) ); - // Subregister 15 of Multireg perf_counter_hart_select - // R[perf_counter_hart_select_15]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_perf_counter_hart_select_15 ( - .clk_i (clk_i), - .rst_ni(rst_ni), - - // from register interface - .we(perf_counter_hart_select_15_we), - .wd(perf_counter_hart_select_15_wd), - // from internal hardware - .de(1'b0), - .d ('0), - - // to internal hardware - .qe(), - .q (reg2hw.perf_counter_hart_select[15].q), - - // to register interface (read) - .qs(perf_counter_hart_select_15_qs) + // F[metric_15]: 31:16 + prim_subreg_ext #( + .DW(16) + ) u_perf_cnt_sel_15_metric_15 ( + .re (perf_cnt_sel_15_metric_15_re), + .we (perf_cnt_sel_15_metric_15_we), + .wd (perf_cnt_sel_15_metric_15_wd), + .d (hw2reg.perf_cnt_sel[15].metric.d), + .qre(), + .qe (reg2hw.perf_cnt_sel[15].metric.qe), + .q (reg2hw.perf_cnt_sel[15].metric.q), + .qs (perf_cnt_sel_15_metric_15_qs) ); - // Subregister 0 of Multireg perf_counter - // R[perf_counter_0]: V(True) + + // Subregister 0 of Multireg perf_cnt + // R[perf_cnt_0]: V(True) prim_subreg_ext #( .DW(48) - ) u_perf_counter_0 ( - .re (perf_counter_0_re), - .we (perf_counter_0_we), - .wd (perf_counter_0_wd), - .d (hw2reg.perf_counter[0].d), + ) u_perf_cnt_0 ( + .re (perf_cnt_0_re), + .we (perf_cnt_0_we), + .wd (perf_cnt_0_wd), + .d (hw2reg.perf_cnt[0].d), .qre(), - .qe (reg2hw.perf_counter[0].qe), - .q (reg2hw.perf_counter[0].q), - .qs (perf_counter_0_qs) + .qe (reg2hw.perf_cnt[0].qe), + .q (reg2hw.perf_cnt[0].q), + .qs (perf_cnt_0_qs) ); - // Subregister 1 of Multireg perf_counter - // R[perf_counter_1]: V(True) + // Subregister 1 of Multireg perf_cnt + // R[perf_cnt_1]: V(True) prim_subreg_ext #( .DW(48) - ) u_perf_counter_1 ( - .re (perf_counter_1_re), - .we (perf_counter_1_we), - .wd (perf_counter_1_wd), - .d (hw2reg.perf_counter[1].d), + ) u_perf_cnt_1 ( + .re (perf_cnt_1_re), + .we (perf_cnt_1_we), + .wd (perf_cnt_1_wd), + .d (hw2reg.perf_cnt[1].d), .qre(), - .qe (reg2hw.perf_counter[1].qe), - .q (reg2hw.perf_counter[1].q), - .qs (perf_counter_1_qs) + .qe (reg2hw.perf_cnt[1].qe), + .q (reg2hw.perf_cnt[1].q), + .qs (perf_cnt_1_qs) ); - // Subregister 2 of Multireg perf_counter - // R[perf_counter_2]: V(True) + // Subregister 2 of Multireg perf_cnt + // R[perf_cnt_2]: V(True) prim_subreg_ext #( .DW(48) - ) u_perf_counter_2 ( - .re (perf_counter_2_re), - .we (perf_counter_2_we), - .wd (perf_counter_2_wd), - .d (hw2reg.perf_counter[2].d), + ) u_perf_cnt_2 ( + .re (perf_cnt_2_re), + .we (perf_cnt_2_we), + .wd (perf_cnt_2_wd), + .d (hw2reg.perf_cnt[2].d), .qre(), - .qe (reg2hw.perf_counter[2].qe), - .q (reg2hw.perf_counter[2].q), - .qs (perf_counter_2_qs) + .qe (reg2hw.perf_cnt[2].qe), + .q (reg2hw.perf_cnt[2].q), + .qs (perf_cnt_2_qs) ); - // Subregister 3 of Multireg perf_counter - // R[perf_counter_3]: V(True) + // Subregister 3 of Multireg perf_cnt + // R[perf_cnt_3]: V(True) prim_subreg_ext #( .DW(48) - ) u_perf_counter_3 ( - .re (perf_counter_3_re), - .we (perf_counter_3_we), - .wd (perf_counter_3_wd), - .d (hw2reg.perf_counter[3].d), + ) u_perf_cnt_3 ( + .re (perf_cnt_3_re), + .we (perf_cnt_3_we), + .wd (perf_cnt_3_wd), + .d (hw2reg.perf_cnt[3].d), .qre(), - .qe (reg2hw.perf_counter[3].qe), - .q (reg2hw.perf_counter[3].q), - .qs (perf_counter_3_qs) + .qe (reg2hw.perf_cnt[3].qe), + .q (reg2hw.perf_cnt[3].q), + .qs (perf_cnt_3_qs) ); - // Subregister 4 of Multireg perf_counter - // R[perf_counter_4]: V(True) + // Subregister 4 of Multireg perf_cnt + // R[perf_cnt_4]: V(True) prim_subreg_ext #( .DW(48) - ) u_perf_counter_4 ( - .re (perf_counter_4_re), - .we (perf_counter_4_we), - .wd (perf_counter_4_wd), - .d (hw2reg.perf_counter[4].d), + ) u_perf_cnt_4 ( + .re (perf_cnt_4_re), + .we (perf_cnt_4_we), + .wd (perf_cnt_4_wd), + .d (hw2reg.perf_cnt[4].d), .qre(), - .qe (reg2hw.perf_counter[4].qe), - .q (reg2hw.perf_counter[4].q), - .qs (perf_counter_4_qs) + .qe (reg2hw.perf_cnt[4].qe), + .q (reg2hw.perf_cnt[4].q), + .qs (perf_cnt_4_qs) ); - // Subregister 5 of Multireg perf_counter - // R[perf_counter_5]: V(True) + // Subregister 5 of Multireg perf_cnt + // R[perf_cnt_5]: V(True) prim_subreg_ext #( .DW(48) - ) u_perf_counter_5 ( - .re (perf_counter_5_re), - .we (perf_counter_5_we), - .wd (perf_counter_5_wd), - .d (hw2reg.perf_counter[5].d), + ) u_perf_cnt_5 ( + .re (perf_cnt_5_re), + .we (perf_cnt_5_we), + .wd (perf_cnt_5_wd), + .d (hw2reg.perf_cnt[5].d), .qre(), - .qe (reg2hw.perf_counter[5].qe), - .q (reg2hw.perf_counter[5].q), - .qs (perf_counter_5_qs) + .qe (reg2hw.perf_cnt[5].qe), + .q (reg2hw.perf_cnt[5].q), + .qs (perf_cnt_5_qs) ); - // Subregister 6 of Multireg perf_counter - // R[perf_counter_6]: V(True) + // Subregister 6 of Multireg perf_cnt + // R[perf_cnt_6]: V(True) prim_subreg_ext #( .DW(48) - ) u_perf_counter_6 ( - .re (perf_counter_6_re), - .we (perf_counter_6_we), - .wd (perf_counter_6_wd), - .d (hw2reg.perf_counter[6].d), + ) u_perf_cnt_6 ( + .re (perf_cnt_6_re), + .we (perf_cnt_6_we), + .wd (perf_cnt_6_wd), + .d (hw2reg.perf_cnt[6].d), .qre(), - .qe (reg2hw.perf_counter[6].qe), - .q (reg2hw.perf_counter[6].q), - .qs (perf_counter_6_qs) + .qe (reg2hw.perf_cnt[6].qe), + .q (reg2hw.perf_cnt[6].q), + .qs (perf_cnt_6_qs) ); - // Subregister 7 of Multireg perf_counter - // R[perf_counter_7]: V(True) + // Subregister 7 of Multireg perf_cnt + // R[perf_cnt_7]: V(True) prim_subreg_ext #( .DW(48) - ) u_perf_counter_7 ( - .re (perf_counter_7_re), - .we (perf_counter_7_we), - .wd (perf_counter_7_wd), - .d (hw2reg.perf_counter[7].d), + ) u_perf_cnt_7 ( + .re (perf_cnt_7_re), + .we (perf_cnt_7_we), + .wd (perf_cnt_7_wd), + .d (hw2reg.perf_cnt[7].d), .qre(), - .qe (reg2hw.perf_counter[7].qe), - .q (reg2hw.perf_counter[7].q), - .qs (perf_counter_7_qs) + .qe (reg2hw.perf_cnt[7].qe), + .q (reg2hw.perf_cnt[7].q), + .qs (perf_cnt_7_qs) ); - // Subregister 8 of Multireg perf_counter - // R[perf_counter_8]: V(True) + // Subregister 8 of Multireg perf_cnt + // R[perf_cnt_8]: V(True) prim_subreg_ext #( .DW(48) - ) u_perf_counter_8 ( - .re (perf_counter_8_re), - .we (perf_counter_8_we), - .wd (perf_counter_8_wd), - .d (hw2reg.perf_counter[8].d), + ) u_perf_cnt_8 ( + .re (perf_cnt_8_re), + .we (perf_cnt_8_we), + .wd (perf_cnt_8_wd), + .d (hw2reg.perf_cnt[8].d), .qre(), - .qe (reg2hw.perf_counter[8].qe), - .q (reg2hw.perf_counter[8].q), - .qs (perf_counter_8_qs) + .qe (reg2hw.perf_cnt[8].qe), + .q (reg2hw.perf_cnt[8].q), + .qs (perf_cnt_8_qs) ); - // Subregister 9 of Multireg perf_counter - // R[perf_counter_9]: V(True) + // Subregister 9 of Multireg perf_cnt + // R[perf_cnt_9]: V(True) prim_subreg_ext #( .DW(48) - ) u_perf_counter_9 ( - .re (perf_counter_9_re), - .we (perf_counter_9_we), - .wd (perf_counter_9_wd), - .d (hw2reg.perf_counter[9].d), + ) u_perf_cnt_9 ( + .re (perf_cnt_9_re), + .we (perf_cnt_9_we), + .wd (perf_cnt_9_wd), + .d (hw2reg.perf_cnt[9].d), .qre(), - .qe (reg2hw.perf_counter[9].qe), - .q (reg2hw.perf_counter[9].q), - .qs (perf_counter_9_qs) + .qe (reg2hw.perf_cnt[9].qe), + .q (reg2hw.perf_cnt[9].q), + .qs (perf_cnt_9_qs) ); - // Subregister 10 of Multireg perf_counter - // R[perf_counter_10]: V(True) + // Subregister 10 of Multireg perf_cnt + // R[perf_cnt_10]: V(True) prim_subreg_ext #( .DW(48) - ) u_perf_counter_10 ( - .re (perf_counter_10_re), - .we (perf_counter_10_we), - .wd (perf_counter_10_wd), - .d (hw2reg.perf_counter[10].d), + ) u_perf_cnt_10 ( + .re (perf_cnt_10_re), + .we (perf_cnt_10_we), + .wd (perf_cnt_10_wd), + .d (hw2reg.perf_cnt[10].d), .qre(), - .qe (reg2hw.perf_counter[10].qe), - .q (reg2hw.perf_counter[10].q), - .qs (perf_counter_10_qs) + .qe (reg2hw.perf_cnt[10].qe), + .q (reg2hw.perf_cnt[10].q), + .qs (perf_cnt_10_qs) ); - // Subregister 11 of Multireg perf_counter - // R[perf_counter_11]: V(True) + // Subregister 11 of Multireg perf_cnt + // R[perf_cnt_11]: V(True) prim_subreg_ext #( .DW(48) - ) u_perf_counter_11 ( - .re (perf_counter_11_re), - .we (perf_counter_11_we), - .wd (perf_counter_11_wd), - .d (hw2reg.perf_counter[11].d), + ) u_perf_cnt_11 ( + .re (perf_cnt_11_re), + .we (perf_cnt_11_we), + .wd (perf_cnt_11_wd), + .d (hw2reg.perf_cnt[11].d), .qre(), - .qe (reg2hw.perf_counter[11].qe), - .q (reg2hw.perf_counter[11].q), - .qs (perf_counter_11_qs) + .qe (reg2hw.perf_cnt[11].qe), + .q (reg2hw.perf_cnt[11].q), + .qs (perf_cnt_11_qs) ); - // Subregister 12 of Multireg perf_counter - // R[perf_counter_12]: V(True) + // Subregister 12 of Multireg perf_cnt + // R[perf_cnt_12]: V(True) prim_subreg_ext #( .DW(48) - ) u_perf_counter_12 ( - .re (perf_counter_12_re), - .we (perf_counter_12_we), - .wd (perf_counter_12_wd), - .d (hw2reg.perf_counter[12].d), + ) u_perf_cnt_12 ( + .re (perf_cnt_12_re), + .we (perf_cnt_12_we), + .wd (perf_cnt_12_wd), + .d (hw2reg.perf_cnt[12].d), .qre(), - .qe (reg2hw.perf_counter[12].qe), - .q (reg2hw.perf_counter[12].q), - .qs (perf_counter_12_qs) + .qe (reg2hw.perf_cnt[12].qe), + .q (reg2hw.perf_cnt[12].q), + .qs (perf_cnt_12_qs) ); - // Subregister 13 of Multireg perf_counter - // R[perf_counter_13]: V(True) + // Subregister 13 of Multireg perf_cnt + // R[perf_cnt_13]: V(True) prim_subreg_ext #( .DW(48) - ) u_perf_counter_13 ( - .re (perf_counter_13_re), - .we (perf_counter_13_we), - .wd (perf_counter_13_wd), - .d (hw2reg.perf_counter[13].d), + ) u_perf_cnt_13 ( + .re (perf_cnt_13_re), + .we (perf_cnt_13_we), + .wd (perf_cnt_13_wd), + .d (hw2reg.perf_cnt[13].d), .qre(), - .qe (reg2hw.perf_counter[13].qe), - .q (reg2hw.perf_counter[13].q), - .qs (perf_counter_13_qs) + .qe (reg2hw.perf_cnt[13].qe), + .q (reg2hw.perf_cnt[13].q), + .qs (perf_cnt_13_qs) ); - // Subregister 14 of Multireg perf_counter - // R[perf_counter_14]: V(True) + // Subregister 14 of Multireg perf_cnt + // R[perf_cnt_14]: V(True) prim_subreg_ext #( .DW(48) - ) u_perf_counter_14 ( - .re (perf_counter_14_re), - .we (perf_counter_14_we), - .wd (perf_counter_14_wd), - .d (hw2reg.perf_counter[14].d), + ) u_perf_cnt_14 ( + .re (perf_cnt_14_re), + .we (perf_cnt_14_we), + .wd (perf_cnt_14_wd), + .d (hw2reg.perf_cnt[14].d), .qre(), - .qe (reg2hw.perf_counter[14].qe), - .q (reg2hw.perf_counter[14].q), - .qs (perf_counter_14_qs) + .qe (reg2hw.perf_cnt[14].qe), + .q (reg2hw.perf_cnt[14].q), + .qs (perf_cnt_14_qs) ); - // Subregister 15 of Multireg perf_counter - // R[perf_counter_15]: V(True) + // Subregister 15 of Multireg perf_cnt + // R[perf_cnt_15]: V(True) prim_subreg_ext #( .DW(48) - ) u_perf_counter_15 ( - .re (perf_counter_15_re), - .we (perf_counter_15_we), - .wd (perf_counter_15_wd), - .d (hw2reg.perf_counter[15].d), + ) u_perf_cnt_15 ( + .re (perf_cnt_15_re), + .we (perf_cnt_15_we), + .wd (perf_cnt_15_wd), + .d (hw2reg.perf_cnt[15].d), .qre(), - .qe (reg2hw.perf_counter[15].qe), - .q (reg2hw.perf_counter[15].q), - .qs (perf_counter_15_qs) + .qe (reg2hw.perf_cnt[15].qe), + .q (reg2hw.perf_cnt[15].q), + .qs (perf_cnt_15_qs) ); @@ -1762,77 +1616,61 @@ module snitch_cluster_peripheral_reg_top #( - logic [67:0] addr_hit; + logic [51:0] addr_hit; always_comb begin addr_hit = '0; - addr_hit[0] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_OFFSET); - addr_hit[1] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_OFFSET); - addr_hit[2] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_OFFSET); - addr_hit[3] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_OFFSET); - addr_hit[4] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_OFFSET); - addr_hit[5] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_OFFSET); - addr_hit[6] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_OFFSET); - addr_hit[7] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_OFFSET); - addr_hit[8] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_OFFSET); - addr_hit[9] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_OFFSET); - addr_hit[10] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_OFFSET); - addr_hit[11] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_OFFSET); - addr_hit[12] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_OFFSET); - addr_hit[13] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_OFFSET); - addr_hit[14] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_OFFSET); - addr_hit[15] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_OFFSET); - addr_hit[16] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_0_OFFSET); - addr_hit[17] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_1_OFFSET); - addr_hit[18] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_2_OFFSET); - addr_hit[19] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_3_OFFSET); - addr_hit[20] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_4_OFFSET); - addr_hit[21] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_5_OFFSET); - addr_hit[22] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_6_OFFSET); - addr_hit[23] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_7_OFFSET); - addr_hit[24] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_8_OFFSET); - addr_hit[25] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_9_OFFSET); - addr_hit[26] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_10_OFFSET); - addr_hit[27] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_11_OFFSET); - addr_hit[28] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_12_OFFSET); - addr_hit[29] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_13_OFFSET); - addr_hit[30] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_14_OFFSET); - addr_hit[31] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_SELECT_15_OFFSET); - addr_hit[32] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_0_OFFSET); - addr_hit[33] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_1_OFFSET); - addr_hit[34] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_2_OFFSET); - addr_hit[35] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_3_OFFSET); - addr_hit[36] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_4_OFFSET); - addr_hit[37] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_5_OFFSET); - addr_hit[38] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_6_OFFSET); - addr_hit[39] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_7_OFFSET); - addr_hit[40] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_8_OFFSET); - addr_hit[41] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_9_OFFSET); - addr_hit[42] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_10_OFFSET); - addr_hit[43] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_11_OFFSET); - addr_hit[44] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_12_OFFSET); - addr_hit[45] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_13_OFFSET); - addr_hit[46] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_14_OFFSET); - addr_hit[47] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_HART_SELECT_15_OFFSET); - addr_hit[48] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_0_OFFSET); - addr_hit[49] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_1_OFFSET); - addr_hit[50] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_2_OFFSET); - addr_hit[51] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_3_OFFSET); - addr_hit[52] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_4_OFFSET); - addr_hit[53] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_5_OFFSET); - addr_hit[54] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_6_OFFSET); - addr_hit[55] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_7_OFFSET); - addr_hit[56] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_8_OFFSET); - addr_hit[57] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_9_OFFSET); - addr_hit[58] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_10_OFFSET); - addr_hit[59] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_11_OFFSET); - addr_hit[60] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_12_OFFSET); - addr_hit[61] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_13_OFFSET); - addr_hit[62] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_14_OFFSET); - addr_hit[63] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_15_OFFSET); - addr_hit[64] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_OFFSET); - addr_hit[65] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_OFFSET); - addr_hit[66] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_OFFSET); - addr_hit[67] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET); + addr_hit[0] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0_OFFSET); + addr_hit[1] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_1_OFFSET); + addr_hit[2] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_2_OFFSET); + addr_hit[3] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_3_OFFSET); + addr_hit[4] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_4_OFFSET); + addr_hit[5] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_5_OFFSET); + addr_hit[6] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_6_OFFSET); + addr_hit[7] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_7_OFFSET); + addr_hit[8] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_8_OFFSET); + addr_hit[9] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_9_OFFSET); + addr_hit[10] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_10_OFFSET); + addr_hit[11] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_11_OFFSET); + addr_hit[12] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_12_OFFSET); + addr_hit[13] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_13_OFFSET); + addr_hit[14] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_14_OFFSET); + addr_hit[15] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_15_OFFSET); + addr_hit[16] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_OFFSET); + addr_hit[17] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_1_OFFSET); + addr_hit[18] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_2_OFFSET); + addr_hit[19] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_3_OFFSET); + addr_hit[20] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_4_OFFSET); + addr_hit[21] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_5_OFFSET); + addr_hit[22] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_6_OFFSET); + addr_hit[23] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_7_OFFSET); + addr_hit[24] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_8_OFFSET); + addr_hit[25] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_9_OFFSET); + addr_hit[26] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_10_OFFSET); + addr_hit[27] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_11_OFFSET); + addr_hit[28] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_12_OFFSET); + addr_hit[29] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_13_OFFSET); + addr_hit[30] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_14_OFFSET); + addr_hit[31] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_15_OFFSET); + addr_hit[32] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_0_OFFSET); + addr_hit[33] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_1_OFFSET); + addr_hit[34] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_2_OFFSET); + addr_hit[35] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_3_OFFSET); + addr_hit[36] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_4_OFFSET); + addr_hit[37] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_5_OFFSET); + addr_hit[38] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_6_OFFSET); + addr_hit[39] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_7_OFFSET); + addr_hit[40] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_8_OFFSET); + addr_hit[41] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_9_OFFSET); + addr_hit[42] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_10_OFFSET); + addr_hit[43] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_11_OFFSET); + addr_hit[44] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_12_OFFSET); + addr_hit[45] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13_OFFSET); + addr_hit[46] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14_OFFSET); + addr_hit[47] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15_OFFSET); + addr_hit[48] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_OFFSET); + addr_hit[49] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_OFFSET); + addr_hit[50] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_OFFSET); + addr_hit[51] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0; @@ -1891,258 +1729,258 @@ module snitch_cluster_peripheral_reg_top #( (addr_hit[48] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[48] & ~reg_be))) | (addr_hit[49] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[49] & ~reg_be))) | (addr_hit[50] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[50] & ~reg_be))) | - (addr_hit[51] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[51] & ~reg_be))) | - (addr_hit[52] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[52] & ~reg_be))) | - (addr_hit[53] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[53] & ~reg_be))) | - (addr_hit[54] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[54] & ~reg_be))) | - (addr_hit[55] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[55] & ~reg_be))) | - (addr_hit[56] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[56] & ~reg_be))) | - (addr_hit[57] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[57] & ~reg_be))) | - (addr_hit[58] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[58] & ~reg_be))) | - (addr_hit[59] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[59] & ~reg_be))) | - (addr_hit[60] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[60] & ~reg_be))) | - (addr_hit[61] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[61] & ~reg_be))) | - (addr_hit[62] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[62] & ~reg_be))) | - (addr_hit[63] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[63] & ~reg_be))) | - (addr_hit[64] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[64] & ~reg_be))) | - (addr_hit[65] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[65] & ~reg_be))) | - (addr_hit[66] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[66] & ~reg_be))) | - (addr_hit[67] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[67] & ~reg_be))))); + (addr_hit[51] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[51] & ~reg_be))))); end - assign perf_counter_enable_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_wd = reg_wdata[0]; + assign perf_cnt_en_0_we = addr_hit[0] & reg_we & !reg_error; + assign perf_cnt_en_0_wd = reg_wdata[0]; - assign perf_counter_enable_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_wd = reg_wdata[0]; + assign perf_cnt_en_1_we = addr_hit[1] & reg_we & !reg_error; + assign perf_cnt_en_1_wd = reg_wdata[0]; - assign perf_counter_enable_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_wd = reg_wdata[0]; + assign perf_cnt_en_2_we = addr_hit[2] & reg_we & !reg_error; + assign perf_cnt_en_2_wd = reg_wdata[0]; - assign perf_counter_enable_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_wd = reg_wdata[0]; + assign perf_cnt_en_3_we = addr_hit[3] & reg_we & !reg_error; + assign perf_cnt_en_3_wd = reg_wdata[0]; - assign perf_counter_enable_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_wd = reg_wdata[0]; + assign perf_cnt_en_4_we = addr_hit[4] & reg_we & !reg_error; + assign perf_cnt_en_4_wd = reg_wdata[0]; - assign perf_counter_enable_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_wd = reg_wdata[0]; + assign perf_cnt_en_5_we = addr_hit[5] & reg_we & !reg_error; + assign perf_cnt_en_5_wd = reg_wdata[0]; - assign perf_counter_enable_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_wd = reg_wdata[0]; + assign perf_cnt_en_6_we = addr_hit[6] & reg_we & !reg_error; + assign perf_cnt_en_6_wd = reg_wdata[0]; - assign perf_counter_enable_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_wd = reg_wdata[0]; + assign perf_cnt_en_7_we = addr_hit[7] & reg_we & !reg_error; + assign perf_cnt_en_7_wd = reg_wdata[0]; - assign perf_counter_enable_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_wd = reg_wdata[0]; + assign perf_cnt_en_8_we = addr_hit[8] & reg_we & !reg_error; + assign perf_cnt_en_8_wd = reg_wdata[0]; - assign perf_counter_enable_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_wd = reg_wdata[0]; + assign perf_cnt_en_9_we = addr_hit[9] & reg_we & !reg_error; + assign perf_cnt_en_9_wd = reg_wdata[0]; - assign perf_counter_enable_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_wd = reg_wdata[0]; + assign perf_cnt_en_10_we = addr_hit[10] & reg_we & !reg_error; + assign perf_cnt_en_10_wd = reg_wdata[0]; - assign perf_counter_enable_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_wd = reg_wdata[0]; + assign perf_cnt_en_11_we = addr_hit[11] & reg_we & !reg_error; + assign perf_cnt_en_11_wd = reg_wdata[0]; - assign perf_counter_enable_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_wd = reg_wdata[0]; + assign perf_cnt_en_12_we = addr_hit[12] & reg_we & !reg_error; + assign perf_cnt_en_12_wd = reg_wdata[0]; - assign perf_counter_enable_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_wd = reg_wdata[0]; + assign perf_cnt_en_13_we = addr_hit[13] & reg_we & !reg_error; + assign perf_cnt_en_13_wd = reg_wdata[0]; - assign perf_counter_enable_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_wd = reg_wdata[0]; + assign perf_cnt_en_14_we = addr_hit[14] & reg_we & !reg_error; + assign perf_cnt_en_14_wd = reg_wdata[0]; - assign perf_counter_enable_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_wd = reg_wdata[0]; + assign perf_cnt_en_15_we = addr_hit[15] & reg_we & !reg_error; + assign perf_cnt_en_15_wd = reg_wdata[0]; - assign perf_counter_select_0_we = addr_hit[16] & reg_we & !reg_error; - assign perf_counter_select_0_wd = reg_wdata[9:0]; - assign perf_counter_select_0_re = addr_hit[16] & reg_re & !reg_error; + assign perf_cnt_sel_0_hart_0_we = addr_hit[16] & reg_we & !reg_error; + assign perf_cnt_sel_0_hart_0_wd = reg_wdata[15:0]; + assign perf_cnt_sel_0_hart_0_re = addr_hit[16] & reg_re & !reg_error; - assign perf_counter_select_1_we = addr_hit[17] & reg_we & !reg_error; - assign perf_counter_select_1_wd = reg_wdata[9:0]; - assign perf_counter_select_1_re = addr_hit[17] & reg_re & !reg_error; + assign perf_cnt_sel_0_metric_0_we = addr_hit[16] & reg_we & !reg_error; + assign perf_cnt_sel_0_metric_0_wd = reg_wdata[31:16]; + assign perf_cnt_sel_0_metric_0_re = addr_hit[16] & reg_re & !reg_error; - assign perf_counter_select_2_we = addr_hit[18] & reg_we & !reg_error; - assign perf_counter_select_2_wd = reg_wdata[9:0]; - assign perf_counter_select_2_re = addr_hit[18] & reg_re & !reg_error; + assign perf_cnt_sel_1_hart_1_we = addr_hit[17] & reg_we & !reg_error; + assign perf_cnt_sel_1_hart_1_wd = reg_wdata[15:0]; + assign perf_cnt_sel_1_hart_1_re = addr_hit[17] & reg_re & !reg_error; - assign perf_counter_select_3_we = addr_hit[19] & reg_we & !reg_error; - assign perf_counter_select_3_wd = reg_wdata[9:0]; - assign perf_counter_select_3_re = addr_hit[19] & reg_re & !reg_error; + assign perf_cnt_sel_1_metric_1_we = addr_hit[17] & reg_we & !reg_error; + assign perf_cnt_sel_1_metric_1_wd = reg_wdata[31:16]; + assign perf_cnt_sel_1_metric_1_re = addr_hit[17] & reg_re & !reg_error; - assign perf_counter_select_4_we = addr_hit[20] & reg_we & !reg_error; - assign perf_counter_select_4_wd = reg_wdata[9:0]; - assign perf_counter_select_4_re = addr_hit[20] & reg_re & !reg_error; + assign perf_cnt_sel_2_hart_2_we = addr_hit[18] & reg_we & !reg_error; + assign perf_cnt_sel_2_hart_2_wd = reg_wdata[15:0]; + assign perf_cnt_sel_2_hart_2_re = addr_hit[18] & reg_re & !reg_error; - assign perf_counter_select_5_we = addr_hit[21] & reg_we & !reg_error; - assign perf_counter_select_5_wd = reg_wdata[9:0]; - assign perf_counter_select_5_re = addr_hit[21] & reg_re & !reg_error; + assign perf_cnt_sel_2_metric_2_we = addr_hit[18] & reg_we & !reg_error; + assign perf_cnt_sel_2_metric_2_wd = reg_wdata[31:16]; + assign perf_cnt_sel_2_metric_2_re = addr_hit[18] & reg_re & !reg_error; - assign perf_counter_select_6_we = addr_hit[22] & reg_we & !reg_error; - assign perf_counter_select_6_wd = reg_wdata[9:0]; - assign perf_counter_select_6_re = addr_hit[22] & reg_re & !reg_error; + assign perf_cnt_sel_3_hart_3_we = addr_hit[19] & reg_we & !reg_error; + assign perf_cnt_sel_3_hart_3_wd = reg_wdata[15:0]; + assign perf_cnt_sel_3_hart_3_re = addr_hit[19] & reg_re & !reg_error; - assign perf_counter_select_7_we = addr_hit[23] & reg_we & !reg_error; - assign perf_counter_select_7_wd = reg_wdata[9:0]; - assign perf_counter_select_7_re = addr_hit[23] & reg_re & !reg_error; + assign perf_cnt_sel_3_metric_3_we = addr_hit[19] & reg_we & !reg_error; + assign perf_cnt_sel_3_metric_3_wd = reg_wdata[31:16]; + assign perf_cnt_sel_3_metric_3_re = addr_hit[19] & reg_re & !reg_error; - assign perf_counter_select_8_we = addr_hit[24] & reg_we & !reg_error; - assign perf_counter_select_8_wd = reg_wdata[9:0]; - assign perf_counter_select_8_re = addr_hit[24] & reg_re & !reg_error; + assign perf_cnt_sel_4_hart_4_we = addr_hit[20] & reg_we & !reg_error; + assign perf_cnt_sel_4_hart_4_wd = reg_wdata[15:0]; + assign perf_cnt_sel_4_hart_4_re = addr_hit[20] & reg_re & !reg_error; - assign perf_counter_select_9_we = addr_hit[25] & reg_we & !reg_error; - assign perf_counter_select_9_wd = reg_wdata[9:0]; - assign perf_counter_select_9_re = addr_hit[25] & reg_re & !reg_error; + assign perf_cnt_sel_4_metric_4_we = addr_hit[20] & reg_we & !reg_error; + assign perf_cnt_sel_4_metric_4_wd = reg_wdata[31:16]; + assign perf_cnt_sel_4_metric_4_re = addr_hit[20] & reg_re & !reg_error; - assign perf_counter_select_10_we = addr_hit[26] & reg_we & !reg_error; - assign perf_counter_select_10_wd = reg_wdata[9:0]; - assign perf_counter_select_10_re = addr_hit[26] & reg_re & !reg_error; + assign perf_cnt_sel_5_hart_5_we = addr_hit[21] & reg_we & !reg_error; + assign perf_cnt_sel_5_hart_5_wd = reg_wdata[15:0]; + assign perf_cnt_sel_5_hart_5_re = addr_hit[21] & reg_re & !reg_error; - assign perf_counter_select_11_we = addr_hit[27] & reg_we & !reg_error; - assign perf_counter_select_11_wd = reg_wdata[9:0]; - assign perf_counter_select_11_re = addr_hit[27] & reg_re & !reg_error; + assign perf_cnt_sel_5_metric_5_we = addr_hit[21] & reg_we & !reg_error; + assign perf_cnt_sel_5_metric_5_wd = reg_wdata[31:16]; + assign perf_cnt_sel_5_metric_5_re = addr_hit[21] & reg_re & !reg_error; - assign perf_counter_select_12_we = addr_hit[28] & reg_we & !reg_error; - assign perf_counter_select_12_wd = reg_wdata[9:0]; - assign perf_counter_select_12_re = addr_hit[28] & reg_re & !reg_error; + assign perf_cnt_sel_6_hart_6_we = addr_hit[22] & reg_we & !reg_error; + assign perf_cnt_sel_6_hart_6_wd = reg_wdata[15:0]; + assign perf_cnt_sel_6_hart_6_re = addr_hit[22] & reg_re & !reg_error; - assign perf_counter_select_13_we = addr_hit[29] & reg_we & !reg_error; - assign perf_counter_select_13_wd = reg_wdata[9:0]; - assign perf_counter_select_13_re = addr_hit[29] & reg_re & !reg_error; + assign perf_cnt_sel_6_metric_6_we = addr_hit[22] & reg_we & !reg_error; + assign perf_cnt_sel_6_metric_6_wd = reg_wdata[31:16]; + assign perf_cnt_sel_6_metric_6_re = addr_hit[22] & reg_re & !reg_error; - assign perf_counter_select_14_we = addr_hit[30] & reg_we & !reg_error; - assign perf_counter_select_14_wd = reg_wdata[9:0]; - assign perf_counter_select_14_re = addr_hit[30] & reg_re & !reg_error; + assign perf_cnt_sel_7_hart_7_we = addr_hit[23] & reg_we & !reg_error; + assign perf_cnt_sel_7_hart_7_wd = reg_wdata[15:0]; + assign perf_cnt_sel_7_hart_7_re = addr_hit[23] & reg_re & !reg_error; - assign perf_counter_select_15_we = addr_hit[31] & reg_we & !reg_error; - assign perf_counter_select_15_wd = reg_wdata[9:0]; - assign perf_counter_select_15_re = addr_hit[31] & reg_re & !reg_error; + assign perf_cnt_sel_7_metric_7_we = addr_hit[23] & reg_we & !reg_error; + assign perf_cnt_sel_7_metric_7_wd = reg_wdata[31:16]; + assign perf_cnt_sel_7_metric_7_re = addr_hit[23] & reg_re & !reg_error; - assign perf_counter_hart_select_0_we = addr_hit[32] & reg_we & !reg_error; - assign perf_counter_hart_select_0_wd = reg_wdata[9:0]; + assign perf_cnt_sel_8_hart_8_we = addr_hit[24] & reg_we & !reg_error; + assign perf_cnt_sel_8_hart_8_wd = reg_wdata[15:0]; + assign perf_cnt_sel_8_hart_8_re = addr_hit[24] & reg_re & !reg_error; - assign perf_counter_hart_select_1_we = addr_hit[33] & reg_we & !reg_error; - assign perf_counter_hart_select_1_wd = reg_wdata[9:0]; + assign perf_cnt_sel_8_metric_8_we = addr_hit[24] & reg_we & !reg_error; + assign perf_cnt_sel_8_metric_8_wd = reg_wdata[31:16]; + assign perf_cnt_sel_8_metric_8_re = addr_hit[24] & reg_re & !reg_error; - assign perf_counter_hart_select_2_we = addr_hit[34] & reg_we & !reg_error; - assign perf_counter_hart_select_2_wd = reg_wdata[9:0]; + assign perf_cnt_sel_9_hart_9_we = addr_hit[25] & reg_we & !reg_error; + assign perf_cnt_sel_9_hart_9_wd = reg_wdata[15:0]; + assign perf_cnt_sel_9_hart_9_re = addr_hit[25] & reg_re & !reg_error; - assign perf_counter_hart_select_3_we = addr_hit[35] & reg_we & !reg_error; - assign perf_counter_hart_select_3_wd = reg_wdata[9:0]; + assign perf_cnt_sel_9_metric_9_we = addr_hit[25] & reg_we & !reg_error; + assign perf_cnt_sel_9_metric_9_wd = reg_wdata[31:16]; + assign perf_cnt_sel_9_metric_9_re = addr_hit[25] & reg_re & !reg_error; - assign perf_counter_hart_select_4_we = addr_hit[36] & reg_we & !reg_error; - assign perf_counter_hart_select_4_wd = reg_wdata[9:0]; + assign perf_cnt_sel_10_hart_10_we = addr_hit[26] & reg_we & !reg_error; + assign perf_cnt_sel_10_hart_10_wd = reg_wdata[15:0]; + assign perf_cnt_sel_10_hart_10_re = addr_hit[26] & reg_re & !reg_error; - assign perf_counter_hart_select_5_we = addr_hit[37] & reg_we & !reg_error; - assign perf_counter_hart_select_5_wd = reg_wdata[9:0]; + assign perf_cnt_sel_10_metric_10_we = addr_hit[26] & reg_we & !reg_error; + assign perf_cnt_sel_10_metric_10_wd = reg_wdata[31:16]; + assign perf_cnt_sel_10_metric_10_re = addr_hit[26] & reg_re & !reg_error; - assign perf_counter_hart_select_6_we = addr_hit[38] & reg_we & !reg_error; - assign perf_counter_hart_select_6_wd = reg_wdata[9:0]; + assign perf_cnt_sel_11_hart_11_we = addr_hit[27] & reg_we & !reg_error; + assign perf_cnt_sel_11_hart_11_wd = reg_wdata[15:0]; + assign perf_cnt_sel_11_hart_11_re = addr_hit[27] & reg_re & !reg_error; - assign perf_counter_hart_select_7_we = addr_hit[39] & reg_we & !reg_error; - assign perf_counter_hart_select_7_wd = reg_wdata[9:0]; + assign perf_cnt_sel_11_metric_11_we = addr_hit[27] & reg_we & !reg_error; + assign perf_cnt_sel_11_metric_11_wd = reg_wdata[31:16]; + assign perf_cnt_sel_11_metric_11_re = addr_hit[27] & reg_re & !reg_error; - assign perf_counter_hart_select_8_we = addr_hit[40] & reg_we & !reg_error; - assign perf_counter_hart_select_8_wd = reg_wdata[9:0]; + assign perf_cnt_sel_12_hart_12_we = addr_hit[28] & reg_we & !reg_error; + assign perf_cnt_sel_12_hart_12_wd = reg_wdata[15:0]; + assign perf_cnt_sel_12_hart_12_re = addr_hit[28] & reg_re & !reg_error; - assign perf_counter_hart_select_9_we = addr_hit[41] & reg_we & !reg_error; - assign perf_counter_hart_select_9_wd = reg_wdata[9:0]; + assign perf_cnt_sel_12_metric_12_we = addr_hit[28] & reg_we & !reg_error; + assign perf_cnt_sel_12_metric_12_wd = reg_wdata[31:16]; + assign perf_cnt_sel_12_metric_12_re = addr_hit[28] & reg_re & !reg_error; - assign perf_counter_hart_select_10_we = addr_hit[42] & reg_we & !reg_error; - assign perf_counter_hart_select_10_wd = reg_wdata[9:0]; + assign perf_cnt_sel_13_hart_13_we = addr_hit[29] & reg_we & !reg_error; + assign perf_cnt_sel_13_hart_13_wd = reg_wdata[15:0]; + assign perf_cnt_sel_13_hart_13_re = addr_hit[29] & reg_re & !reg_error; - assign perf_counter_hart_select_11_we = addr_hit[43] & reg_we & !reg_error; - assign perf_counter_hart_select_11_wd = reg_wdata[9:0]; + assign perf_cnt_sel_13_metric_13_we = addr_hit[29] & reg_we & !reg_error; + assign perf_cnt_sel_13_metric_13_wd = reg_wdata[31:16]; + assign perf_cnt_sel_13_metric_13_re = addr_hit[29] & reg_re & !reg_error; - assign perf_counter_hart_select_12_we = addr_hit[44] & reg_we & !reg_error; - assign perf_counter_hart_select_12_wd = reg_wdata[9:0]; + assign perf_cnt_sel_14_hart_14_we = addr_hit[30] & reg_we & !reg_error; + assign perf_cnt_sel_14_hart_14_wd = reg_wdata[15:0]; + assign perf_cnt_sel_14_hart_14_re = addr_hit[30] & reg_re & !reg_error; - assign perf_counter_hart_select_13_we = addr_hit[45] & reg_we & !reg_error; - assign perf_counter_hart_select_13_wd = reg_wdata[9:0]; + assign perf_cnt_sel_14_metric_14_we = addr_hit[30] & reg_we & !reg_error; + assign perf_cnt_sel_14_metric_14_wd = reg_wdata[31:16]; + assign perf_cnt_sel_14_metric_14_re = addr_hit[30] & reg_re & !reg_error; - assign perf_counter_hart_select_14_we = addr_hit[46] & reg_we & !reg_error; - assign perf_counter_hart_select_14_wd = reg_wdata[9:0]; + assign perf_cnt_sel_15_hart_15_we = addr_hit[31] & reg_we & !reg_error; + assign perf_cnt_sel_15_hart_15_wd = reg_wdata[15:0]; + assign perf_cnt_sel_15_hart_15_re = addr_hit[31] & reg_re & !reg_error; - assign perf_counter_hart_select_15_we = addr_hit[47] & reg_we & !reg_error; - assign perf_counter_hart_select_15_wd = reg_wdata[9:0]; + assign perf_cnt_sel_15_metric_15_we = addr_hit[31] & reg_we & !reg_error; + assign perf_cnt_sel_15_metric_15_wd = reg_wdata[31:16]; + assign perf_cnt_sel_15_metric_15_re = addr_hit[31] & reg_re & !reg_error; - assign perf_counter_0_we = addr_hit[48] & reg_we & !reg_error; - assign perf_counter_0_wd = reg_wdata[47:0]; - assign perf_counter_0_re = addr_hit[48] & reg_re & !reg_error; + assign perf_cnt_0_we = addr_hit[32] & reg_we & !reg_error; + assign perf_cnt_0_wd = reg_wdata[47:0]; + assign perf_cnt_0_re = addr_hit[32] & reg_re & !reg_error; - assign perf_counter_1_we = addr_hit[49] & reg_we & !reg_error; - assign perf_counter_1_wd = reg_wdata[47:0]; - assign perf_counter_1_re = addr_hit[49] & reg_re & !reg_error; + assign perf_cnt_1_we = addr_hit[33] & reg_we & !reg_error; + assign perf_cnt_1_wd = reg_wdata[47:0]; + assign perf_cnt_1_re = addr_hit[33] & reg_re & !reg_error; - assign perf_counter_2_we = addr_hit[50] & reg_we & !reg_error; - assign perf_counter_2_wd = reg_wdata[47:0]; - assign perf_counter_2_re = addr_hit[50] & reg_re & !reg_error; + assign perf_cnt_2_we = addr_hit[34] & reg_we & !reg_error; + assign perf_cnt_2_wd = reg_wdata[47:0]; + assign perf_cnt_2_re = addr_hit[34] & reg_re & !reg_error; - assign perf_counter_3_we = addr_hit[51] & reg_we & !reg_error; - assign perf_counter_3_wd = reg_wdata[47:0]; - assign perf_counter_3_re = addr_hit[51] & reg_re & !reg_error; + assign perf_cnt_3_we = addr_hit[35] & reg_we & !reg_error; + assign perf_cnt_3_wd = reg_wdata[47:0]; + assign perf_cnt_3_re = addr_hit[35] & reg_re & !reg_error; - assign perf_counter_4_we = addr_hit[52] & reg_we & !reg_error; - assign perf_counter_4_wd = reg_wdata[47:0]; - assign perf_counter_4_re = addr_hit[52] & reg_re & !reg_error; + assign perf_cnt_4_we = addr_hit[36] & reg_we & !reg_error; + assign perf_cnt_4_wd = reg_wdata[47:0]; + assign perf_cnt_4_re = addr_hit[36] & reg_re & !reg_error; - assign perf_counter_5_we = addr_hit[53] & reg_we & !reg_error; - assign perf_counter_5_wd = reg_wdata[47:0]; - assign perf_counter_5_re = addr_hit[53] & reg_re & !reg_error; + assign perf_cnt_5_we = addr_hit[37] & reg_we & !reg_error; + assign perf_cnt_5_wd = reg_wdata[47:0]; + assign perf_cnt_5_re = addr_hit[37] & reg_re & !reg_error; - assign perf_counter_6_we = addr_hit[54] & reg_we & !reg_error; - assign perf_counter_6_wd = reg_wdata[47:0]; - assign perf_counter_6_re = addr_hit[54] & reg_re & !reg_error; + assign perf_cnt_6_we = addr_hit[38] & reg_we & !reg_error; + assign perf_cnt_6_wd = reg_wdata[47:0]; + assign perf_cnt_6_re = addr_hit[38] & reg_re & !reg_error; - assign perf_counter_7_we = addr_hit[55] & reg_we & !reg_error; - assign perf_counter_7_wd = reg_wdata[47:0]; - assign perf_counter_7_re = addr_hit[55] & reg_re & !reg_error; + assign perf_cnt_7_we = addr_hit[39] & reg_we & !reg_error; + assign perf_cnt_7_wd = reg_wdata[47:0]; + assign perf_cnt_7_re = addr_hit[39] & reg_re & !reg_error; - assign perf_counter_8_we = addr_hit[56] & reg_we & !reg_error; - assign perf_counter_8_wd = reg_wdata[47:0]; - assign perf_counter_8_re = addr_hit[56] & reg_re & !reg_error; + assign perf_cnt_8_we = addr_hit[40] & reg_we & !reg_error; + assign perf_cnt_8_wd = reg_wdata[47:0]; + assign perf_cnt_8_re = addr_hit[40] & reg_re & !reg_error; - assign perf_counter_9_we = addr_hit[57] & reg_we & !reg_error; - assign perf_counter_9_wd = reg_wdata[47:0]; - assign perf_counter_9_re = addr_hit[57] & reg_re & !reg_error; + assign perf_cnt_9_we = addr_hit[41] & reg_we & !reg_error; + assign perf_cnt_9_wd = reg_wdata[47:0]; + assign perf_cnt_9_re = addr_hit[41] & reg_re & !reg_error; - assign perf_counter_10_we = addr_hit[58] & reg_we & !reg_error; - assign perf_counter_10_wd = reg_wdata[47:0]; - assign perf_counter_10_re = addr_hit[58] & reg_re & !reg_error; + assign perf_cnt_10_we = addr_hit[42] & reg_we & !reg_error; + assign perf_cnt_10_wd = reg_wdata[47:0]; + assign perf_cnt_10_re = addr_hit[42] & reg_re & !reg_error; - assign perf_counter_11_we = addr_hit[59] & reg_we & !reg_error; - assign perf_counter_11_wd = reg_wdata[47:0]; - assign perf_counter_11_re = addr_hit[59] & reg_re & !reg_error; + assign perf_cnt_11_we = addr_hit[43] & reg_we & !reg_error; + assign perf_cnt_11_wd = reg_wdata[47:0]; + assign perf_cnt_11_re = addr_hit[43] & reg_re & !reg_error; - assign perf_counter_12_we = addr_hit[60] & reg_we & !reg_error; - assign perf_counter_12_wd = reg_wdata[47:0]; - assign perf_counter_12_re = addr_hit[60] & reg_re & !reg_error; + assign perf_cnt_12_we = addr_hit[44] & reg_we & !reg_error; + assign perf_cnt_12_wd = reg_wdata[47:0]; + assign perf_cnt_12_re = addr_hit[44] & reg_re & !reg_error; - assign perf_counter_13_we = addr_hit[61] & reg_we & !reg_error; - assign perf_counter_13_wd = reg_wdata[47:0]; - assign perf_counter_13_re = addr_hit[61] & reg_re & !reg_error; + assign perf_cnt_13_we = addr_hit[45] & reg_we & !reg_error; + assign perf_cnt_13_wd = reg_wdata[47:0]; + assign perf_cnt_13_re = addr_hit[45] & reg_re & !reg_error; - assign perf_counter_14_we = addr_hit[62] & reg_we & !reg_error; - assign perf_counter_14_wd = reg_wdata[47:0]; - assign perf_counter_14_re = addr_hit[62] & reg_re & !reg_error; + assign perf_cnt_14_we = addr_hit[46] & reg_we & !reg_error; + assign perf_cnt_14_wd = reg_wdata[47:0]; + assign perf_cnt_14_re = addr_hit[46] & reg_re & !reg_error; - assign perf_counter_15_we = addr_hit[63] & reg_we & !reg_error; - assign perf_counter_15_wd = reg_wdata[47:0]; - assign perf_counter_15_re = addr_hit[63] & reg_re & !reg_error; + assign perf_cnt_15_we = addr_hit[47] & reg_we & !reg_error; + assign perf_cnt_15_wd = reg_wdata[47:0]; + assign perf_cnt_15_re = addr_hit[47] & reg_re & !reg_error; - assign cl_clint_set_we = addr_hit[64] & reg_we & !reg_error; + assign cl_clint_set_we = addr_hit[48] & reg_we & !reg_error; assign cl_clint_set_wd = reg_wdata[31:0]; - assign cl_clint_clear_we = addr_hit[65] & reg_we & !reg_error; + assign cl_clint_clear_we = addr_hit[49] & reg_we & !reg_error; assign cl_clint_clear_wd = reg_wdata[31:0]; - assign hw_barrier_re = addr_hit[66] & reg_re & !reg_error; + assign hw_barrier_re = addr_hit[50] & reg_re & !reg_error; - assign icache_prefetch_enable_we = addr_hit[67] & reg_we & !reg_error; + assign icache_prefetch_enable_we = addr_hit[51] & reg_we & !reg_error; assign icache_prefetch_enable_wd = reg_wdata[0]; // Read data return @@ -2150,274 +1988,226 @@ module snitch_cluster_peripheral_reg_top #( reg_rdata_next = '0; unique case (1'b1) addr_hit[0]: begin - reg_rdata_next[0] = perf_counter_enable_0_qs; + reg_rdata_next[0] = perf_cnt_en_0_qs; end addr_hit[1]: begin - reg_rdata_next[0] = perf_counter_enable_1_qs; + reg_rdata_next[0] = perf_cnt_en_1_qs; end addr_hit[2]: begin - reg_rdata_next[0] = perf_counter_enable_2_qs; + reg_rdata_next[0] = perf_cnt_en_2_qs; end addr_hit[3]: begin - reg_rdata_next[0] = perf_counter_enable_3_qs; + reg_rdata_next[0] = perf_cnt_en_3_qs; end addr_hit[4]: begin - reg_rdata_next[0] = perf_counter_enable_4_qs; + reg_rdata_next[0] = perf_cnt_en_4_qs; end addr_hit[5]: begin - reg_rdata_next[0] = perf_counter_enable_5_qs; + reg_rdata_next[0] = perf_cnt_en_5_qs; end addr_hit[6]: begin - reg_rdata_next[0] = perf_counter_enable_6_qs; + reg_rdata_next[0] = perf_cnt_en_6_qs; end addr_hit[7]: begin - reg_rdata_next[0] = perf_counter_enable_7_qs; + reg_rdata_next[0] = perf_cnt_en_7_qs; end addr_hit[8]: begin - reg_rdata_next[0] = perf_counter_enable_8_qs; + reg_rdata_next[0] = perf_cnt_en_8_qs; end addr_hit[9]: begin - reg_rdata_next[0] = perf_counter_enable_9_qs; + reg_rdata_next[0] = perf_cnt_en_9_qs; end addr_hit[10]: begin - reg_rdata_next[0] = perf_counter_enable_10_qs; + reg_rdata_next[0] = perf_cnt_en_10_qs; end addr_hit[11]: begin - reg_rdata_next[0] = perf_counter_enable_11_qs; + reg_rdata_next[0] = perf_cnt_en_11_qs; end addr_hit[12]: begin - reg_rdata_next[0] = perf_counter_enable_12_qs; + reg_rdata_next[0] = perf_cnt_en_12_qs; end addr_hit[13]: begin - reg_rdata_next[0] = perf_counter_enable_13_qs; + reg_rdata_next[0] = perf_cnt_en_13_qs; end addr_hit[14]: begin - reg_rdata_next[0] = perf_counter_enable_14_qs; + reg_rdata_next[0] = perf_cnt_en_14_qs; end addr_hit[15]: begin - reg_rdata_next[0] = perf_counter_enable_15_qs; + reg_rdata_next[0] = perf_cnt_en_15_qs; end addr_hit[16]: begin - reg_rdata_next[9:0] = perf_counter_select_0_qs; + reg_rdata_next[15:0] = perf_cnt_sel_0_hart_0_qs; + reg_rdata_next[31:16] = perf_cnt_sel_0_metric_0_qs; end addr_hit[17]: begin - reg_rdata_next[9:0] = perf_counter_select_1_qs; + reg_rdata_next[15:0] = perf_cnt_sel_1_hart_1_qs; + reg_rdata_next[31:16] = perf_cnt_sel_1_metric_1_qs; end addr_hit[18]: begin - reg_rdata_next[9:0] = perf_counter_select_2_qs; + reg_rdata_next[15:0] = perf_cnt_sel_2_hart_2_qs; + reg_rdata_next[31:16] = perf_cnt_sel_2_metric_2_qs; end addr_hit[19]: begin - reg_rdata_next[9:0] = perf_counter_select_3_qs; + reg_rdata_next[15:0] = perf_cnt_sel_3_hart_3_qs; + reg_rdata_next[31:16] = perf_cnt_sel_3_metric_3_qs; end addr_hit[20]: begin - reg_rdata_next[9:0] = perf_counter_select_4_qs; + reg_rdata_next[15:0] = perf_cnt_sel_4_hart_4_qs; + reg_rdata_next[31:16] = perf_cnt_sel_4_metric_4_qs; end addr_hit[21]: begin - reg_rdata_next[9:0] = perf_counter_select_5_qs; + reg_rdata_next[15:0] = perf_cnt_sel_5_hart_5_qs; + reg_rdata_next[31:16] = perf_cnt_sel_5_metric_5_qs; end addr_hit[22]: begin - reg_rdata_next[9:0] = perf_counter_select_6_qs; + reg_rdata_next[15:0] = perf_cnt_sel_6_hart_6_qs; + reg_rdata_next[31:16] = perf_cnt_sel_6_metric_6_qs; end addr_hit[23]: begin - reg_rdata_next[9:0] = perf_counter_select_7_qs; + reg_rdata_next[15:0] = perf_cnt_sel_7_hart_7_qs; + reg_rdata_next[31:16] = perf_cnt_sel_7_metric_7_qs; end addr_hit[24]: begin - reg_rdata_next[9:0] = perf_counter_select_8_qs; + reg_rdata_next[15:0] = perf_cnt_sel_8_hart_8_qs; + reg_rdata_next[31:16] = perf_cnt_sel_8_metric_8_qs; end addr_hit[25]: begin - reg_rdata_next[9:0] = perf_counter_select_9_qs; + reg_rdata_next[15:0] = perf_cnt_sel_9_hart_9_qs; + reg_rdata_next[31:16] = perf_cnt_sel_9_metric_9_qs; end addr_hit[26]: begin - reg_rdata_next[9:0] = perf_counter_select_10_qs; + reg_rdata_next[15:0] = perf_cnt_sel_10_hart_10_qs; + reg_rdata_next[31:16] = perf_cnt_sel_10_metric_10_qs; end addr_hit[27]: begin - reg_rdata_next[9:0] = perf_counter_select_11_qs; + reg_rdata_next[15:0] = perf_cnt_sel_11_hart_11_qs; + reg_rdata_next[31:16] = perf_cnt_sel_11_metric_11_qs; end addr_hit[28]: begin - reg_rdata_next[9:0] = perf_counter_select_12_qs; + reg_rdata_next[15:0] = perf_cnt_sel_12_hart_12_qs; + reg_rdata_next[31:16] = perf_cnt_sel_12_metric_12_qs; end addr_hit[29]: begin - reg_rdata_next[9:0] = perf_counter_select_13_qs; + reg_rdata_next[15:0] = perf_cnt_sel_13_hart_13_qs; + reg_rdata_next[31:16] = perf_cnt_sel_13_metric_13_qs; end addr_hit[30]: begin - reg_rdata_next[9:0] = perf_counter_select_14_qs; + reg_rdata_next[15:0] = perf_cnt_sel_14_hart_14_qs; + reg_rdata_next[31:16] = perf_cnt_sel_14_metric_14_qs; end addr_hit[31]: begin - reg_rdata_next[9:0] = perf_counter_select_15_qs; + reg_rdata_next[15:0] = perf_cnt_sel_15_hart_15_qs; + reg_rdata_next[31:16] = perf_cnt_sel_15_metric_15_qs; end addr_hit[32]: begin - reg_rdata_next[9:0] = perf_counter_hart_select_0_qs; + reg_rdata_next[47:0] = perf_cnt_0_qs; end addr_hit[33]: begin - reg_rdata_next[9:0] = perf_counter_hart_select_1_qs; + reg_rdata_next[47:0] = perf_cnt_1_qs; end addr_hit[34]: begin - reg_rdata_next[9:0] = perf_counter_hart_select_2_qs; + reg_rdata_next[47:0] = perf_cnt_2_qs; end addr_hit[35]: begin - reg_rdata_next[9:0] = perf_counter_hart_select_3_qs; + reg_rdata_next[47:0] = perf_cnt_3_qs; end addr_hit[36]: begin - reg_rdata_next[9:0] = perf_counter_hart_select_4_qs; + reg_rdata_next[47:0] = perf_cnt_4_qs; end addr_hit[37]: begin - reg_rdata_next[9:0] = perf_counter_hart_select_5_qs; + reg_rdata_next[47:0] = perf_cnt_5_qs; end addr_hit[38]: begin - reg_rdata_next[9:0] = perf_counter_hart_select_6_qs; + reg_rdata_next[47:0] = perf_cnt_6_qs; end addr_hit[39]: begin - reg_rdata_next[9:0] = perf_counter_hart_select_7_qs; + reg_rdata_next[47:0] = perf_cnt_7_qs; end addr_hit[40]: begin - reg_rdata_next[9:0] = perf_counter_hart_select_8_qs; + reg_rdata_next[47:0] = perf_cnt_8_qs; end addr_hit[41]: begin - reg_rdata_next[9:0] = perf_counter_hart_select_9_qs; + reg_rdata_next[47:0] = perf_cnt_9_qs; end addr_hit[42]: begin - reg_rdata_next[9:0] = perf_counter_hart_select_10_qs; + reg_rdata_next[47:0] = perf_cnt_10_qs; end addr_hit[43]: begin - reg_rdata_next[9:0] = perf_counter_hart_select_11_qs; + reg_rdata_next[47:0] = perf_cnt_11_qs; end addr_hit[44]: begin - reg_rdata_next[9:0] = perf_counter_hart_select_12_qs; + reg_rdata_next[47:0] = perf_cnt_12_qs; end addr_hit[45]: begin - reg_rdata_next[9:0] = perf_counter_hart_select_13_qs; + reg_rdata_next[47:0] = perf_cnt_13_qs; end addr_hit[46]: begin - reg_rdata_next[9:0] = perf_counter_hart_select_14_qs; + reg_rdata_next[47:0] = perf_cnt_14_qs; end addr_hit[47]: begin - reg_rdata_next[9:0] = perf_counter_hart_select_15_qs; + reg_rdata_next[47:0] = perf_cnt_15_qs; end addr_hit[48]: begin - reg_rdata_next[47:0] = perf_counter_0_qs; - end - - addr_hit[49]: begin - reg_rdata_next[47:0] = perf_counter_1_qs; - end - - addr_hit[50]: begin - reg_rdata_next[47:0] = perf_counter_2_qs; - end - - addr_hit[51]: begin - reg_rdata_next[47:0] = perf_counter_3_qs; - end - - addr_hit[52]: begin - reg_rdata_next[47:0] = perf_counter_4_qs; - end - - addr_hit[53]: begin - reg_rdata_next[47:0] = perf_counter_5_qs; - end - - addr_hit[54]: begin - reg_rdata_next[47:0] = perf_counter_6_qs; - end - - addr_hit[55]: begin - reg_rdata_next[47:0] = perf_counter_7_qs; - end - - addr_hit[56]: begin - reg_rdata_next[47:0] = perf_counter_8_qs; - end - - addr_hit[57]: begin - reg_rdata_next[47:0] = perf_counter_9_qs; - end - - addr_hit[58]: begin - reg_rdata_next[47:0] = perf_counter_10_qs; - end - - addr_hit[59]: begin - reg_rdata_next[47:0] = perf_counter_11_qs; - end - - addr_hit[60]: begin - reg_rdata_next[47:0] = perf_counter_12_qs; - end - - addr_hit[61]: begin - reg_rdata_next[47:0] = perf_counter_13_qs; - end - - addr_hit[62]: begin - reg_rdata_next[47:0] = perf_counter_14_qs; - end - - addr_hit[63]: begin - reg_rdata_next[47:0] = perf_counter_15_qs; - end - - addr_hit[64]: begin reg_rdata_next[31:0] = '0; end - addr_hit[65]: begin + addr_hit[49]: begin reg_rdata_next[31:0] = '0; end - addr_hit[66]: begin + addr_hit[50]: begin reg_rdata_next[31:0] = hw_barrier_qs; end - addr_hit[67]: begin + addr_hit[51]: begin reg_rdata_next[0] = '0; end @@ -2442,7 +2232,7 @@ module snitch_cluster_peripheral_reg_top #( endmodule module snitch_cluster_peripheral_reg_top_intf #( - parameter int AW = 10, + parameter int AW = 9, localparam int DW = 64 ) ( input logic clk_i,