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ci: Reduce core count for Verilator model
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| // Copyright 2023 ETH Zurich and University of Bologna. | ||
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. | ||
| // SPDX-License-Identifier: Apache-2.0 | ||
|
|
||
| // Cluster configuration for a simple testbench system. | ||
| { | ||
| nr_s1_quadrant: 1, | ||
| s1_quadrant: { | ||
| nr_clusters: 1, | ||
| }, | ||
|
|
||
| cluster: { | ||
| boot_addr: 4096, // 0x1000 | ||
| cluster_base_addr: 268435456, // 0x1000_0000 | ||
| cluster_base_offset: 0, // 0x0 | ||
| cluster_base_hartid: 0, | ||
| addr_width: 48, | ||
| data_width: 64, | ||
| user_width: 5, // clog2(total number of clusters) | ||
| tcdm: { | ||
| size: 128, | ||
| banks: 32, | ||
| }, | ||
| cluster_periph_size: 64, // kB | ||
| zero_mem_size: 64, // kB | ||
| alias_region_enable: true, | ||
| dma_data_width: 512, | ||
| dma_axi_req_fifo_depth: 24, | ||
| dma_req_fifo_depth: 8, | ||
| narrow_trans: 4, | ||
| wide_trans: 32, | ||
| dma_user_width: 1, | ||
| // We don't need Snitch debugging in Occamy | ||
| enable_debug: false, | ||
| // We don't need Snitch (core-internal) virtual memory support | ||
| vm_support: false, | ||
| // Memory configuration inputs | ||
| sram_cfg_expose: true, | ||
| sram_cfg_fields: { | ||
| ema: 3, | ||
| emaw: 2, | ||
| emas: 1 | ||
| }, | ||
| // Timing parameters | ||
| timing: { | ||
| lat_comp_fp32: 2, | ||
| lat_comp_fp64: 3, | ||
| lat_comp_fp16: 1, | ||
| lat_comp_fp16_alt: 1, | ||
| lat_comp_fp8: 1, | ||
| lat_comp_fp8_alt: 1, | ||
| lat_noncomp: 1, | ||
| lat_conv: 2, | ||
| lat_sdotp: 3, | ||
| fpu_pipe_config: "BEFORE", | ||
| narrow_xbar_latency: "CUT_ALL_PORTS", | ||
| wide_xbar_latency: "CUT_ALL_PORTS", | ||
| // Isolate the core. | ||
| register_core_req: true, | ||
| register_core_rsp: true, | ||
| register_offload_req: true, | ||
| register_offload_rsp: true, | ||
| register_fpu_req: true, | ||
| register_ext_narrow: false, | ||
| register_ext_wide: false | ||
| }, | ||
| hives: [ | ||
| // Hive 0 | ||
| { | ||
| icache: { | ||
| size: 8, // total instruction cache size in kByte | ||
| sets: 2, // number of ways | ||
| cacheline: 256 // word size in bits | ||
| }, | ||
| cores: [ | ||
| { $ref: "#/compute_core_template" }, | ||
| { $ref: "#/compute_core_template" }, | ||
| { $ref: "#/compute_core_template" }, | ||
| { $ref: "#/compute_core_template" }, | ||
| { $ref: "#/dma_core_template" }, | ||
| ] | ||
| } | ||
| ] | ||
| }, | ||
| dram: { | ||
| // 0x8000_0000 | ||
| address: 2147483648, | ||
| // 0x8000_0000 | ||
| length: 2147483648 | ||
| }, | ||
| peripherals: { | ||
| clint: { | ||
| // 0xffff_0000 | ||
| address: 4294901760, | ||
| // 0x0000_1000 | ||
| length: 4096 | ||
| }, | ||
| }, | ||
| // Templates. | ||
| compute_core_template: { | ||
| isa: "rv32imafd", | ||
| xssr: true, | ||
| xfrep: true, | ||
| xdma: false, | ||
| xf16: true, | ||
| xf16alt: true, | ||
| xf8: true, | ||
| xf8alt: true, | ||
| xfdotp: true, | ||
| xfvec: true, | ||
| ssr_nr_credits: 4, | ||
| num_int_outstanding_loads: 1, | ||
| num_int_outstanding_mem: 4, | ||
| num_fp_outstanding_loads: 4, | ||
| num_fp_outstanding_mem: 4, | ||
| num_sequencer_instructions: 16, | ||
| num_dtlb_entries: 1, | ||
| num_itlb_entries: 1, | ||
| // SSSR configuration below | ||
| ssr_intersection: true, | ||
| ssr_intersection_triple: [0, 1, 2], | ||
| ssrs: [ | ||
| {indirection: true}, // Master 0 | ||
| {indirection: true}, // Master 1 | ||
| {}, // Slave | ||
| ], | ||
| // Enable division/square root unit | ||
| Xdiv_sqrt: true, | ||
| }, | ||
| dma_core_template: { | ||
| isa: "rv32imafd", | ||
| Xdiv_sqrt: true, | ||
| xdma: true, | ||
| xssr: false, | ||
| xfrep: false, | ||
| xf16: false, | ||
| xf16alt: false, | ||
| xf8: false, | ||
| xf8alt: false, | ||
| xfdotp: false, | ||
| xfvec: false, | ||
| num_int_outstanding_loads: 1, | ||
| num_int_outstanding_mem: 4, | ||
| num_fp_outstanding_loads: 4, | ||
| num_fp_outstanding_mem: 4, | ||
| num_sequencer_instructions: 16, | ||
| num_dtlb_entries: 1, | ||
| num_itlb_entries: 1, | ||
| } | ||
| } |