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* utils/sim: Add MkDocs documentation * utils/sim: Improve extensibility by using `kwargs` in constructors * util/container: Upgrade to Python 3.9.12 * util/container: Install `ca-certificates` to fix curl error 77 * util/container: Install `make` and `gcc` * util/sim: Add per-simulation run directory and dry-run options * target: Selectively disable full RTL visibility and wave logging This is used to speed up simulation time. By default, full RTL visibility in Questasim (+acc flag) is not enabled. By compiling the hardware with DEBUG=ON (`make DEBUG=ON bin/snitch_cluster.vsim`) it is enabled and all waves are logged.
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clang-format | ||
device-tree-compiler | ||
graphviz | ||
python3 | ||
python3-pip | ||
python3-setuptools | ||
python3-wheel | ||
tar |
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::: Simulation |
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::: Simulator |
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::: sim_utils |
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