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Update CI software commands
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@micprog
micprog committed Mar 22, 2024
1 parent f2412a6 commit 59be5f4
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288 changes: 164 additions & 124 deletions .gitlab-ci.yml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,8 +14,9 @@

variables:
GIT_SUBMODULE_STRATEGY: recursive
VSIM: "questa-2023.4-zr vsim"
VSIM_BIN: "questa-2023.4-zr vsim"
QUESTA: "questa-2023.4-zr"
VSIM: "$QUESTA vsim"
VSIM_BIN: "$QUESTA vsim"
RISCV: "/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0"
PULP_RISCV_GCC_TOOLCHAIN: "/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0"

Expand Down Expand Up @@ -55,6 +56,7 @@ build_rtl:
paths:
- target/sim/tb/tb_lib/remote_bitbang/* # we want to reuse bitbang lib
- target/sim/vip/*
- build/questasim/*


lint:
Expand All @@ -77,63 +79,102 @@ lint:
# Use sdk-releases to run all tests
test_sequential_bare:
stage: test
before_script:
- echo "Compiling RTL model and DPI libraries"
- make build
needs: [ build_rtl ]
parallel:
matrix:
- { TEST: dct }
- { TEST: fft2 }
- { TEST: rijndael }
- { TEST: jacobi-2d-imper }
- { TEST: bitDescriptor }
- { TEST: stencil_vect }
- { TEST: keccak }
- { TEST: fir }
- { TEST: stencil }
- { TEST: ipm }
- { TEST: towerofhanoi }
- { TEST: crc32 }
- { TEST: conv2d }
- { TEST: seidel }
- { TEST: fibonacci }
- { TEST: gauss-2d }
- { TEST: aes_cbc }
- { TEST: bubblesort }
- { TEST: fdtd-1d }
- { TEST: jacobi-1d-imper }
- { TEST: fft }
script:
- echo "Running sequential bare tests"
- source sw/pulp-runtime/configs/pulpissimo.sh
- make relink
- source sw/pulp-runtime/configs/pulpissimo_cv32.sh
- export VSIM_PATH=$PWD/build/questasim
- cd sw/regression_tests/sequential_bare_tests && plptest --threads 32 --stdout
- echo "Generating junit test results"
- /usr/sepp/bin/python3.4 -m junit2htmlreport junit-reports/TEST-*.xml
artifacts:
name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
paths:
- sw/regression_tests/sequential_bare_tests/junit-reports/TEST-*.html
- sw/regression_tests/sequential_bare_tests/junit-reports/TEST-*.xml
reports:
junit: sw/regression_tests/sequential_bare_tests/junit-reports/TEST-*.xml
- cd sw/regression_tests/sequential_bare_tests/${TEST}
- make clean all run

test_ml:
stage: test
before_script:
- echo "Compiling RTL model and DPI libraries"
- make build
needs: [ build_rtl ]
parallel:
matrix:
- { TEST: mlDotp }
- { TEST: mlSchur }
- { TEST: mlGemm }
- { TEST: mlSin }
- { TEST: mlSvd }
- { TEST: mlButter }
- { TEST: mlGradDir }
- { TEST: mlRbf }
- { TEST: mlLog }
- { TEST: mlAxpy }
- { TEST: mlGivens }
- { TEST: mlWdotp }
- { TEST: mlDist }
- { TEST: mlGemv }
- { TEST: mlChol }
- { TEST: mlGrad }
- { TEST: mlDct }
script:
- echo "Running ml tests"
- source sw/pulp-runtime/configs/pulpissimo.sh
- make relink
- source sw/pulp-runtime/configs/pulpissimo_cv32.sh
- export VSIM_PATH=$PWD/build/questasim
- cd sw/regression_tests/ml_tests && plptest --threads 32 --stdout
- echo "Generating junit test results"
- /usr/sepp/bin/python3.4 -m junit2htmlreport junit-reports/TEST-*.xml
artifacts:
name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
paths:
- sw/regression_tests/ml_tests/junit-reports/TEST-*.html
- sw/regression_tests/ml_tests/junit-reports/TEST-*.xml
reports:
junit: sw/regression_tests/ml_tests/junit-reports/TEST-*.xml
- cd sw/regression_tests/ml_tests/${TEST}
- make clean all run

test_riscv:
stage: test
before_script:
- echo "Compiling RTL model and DPI libraries"
- make build
needs: [ build_rtl ]
parallel:
matrix:
- { TEST: testBitManipulation }
- { TEST: testVecCmp }
- { TEST: testAddSubNorm }
- { TEST: testMisaligned }
- { TEST: testALU }
- { TEST: testMAC3 }
- { TEST: testEventsFlex }
- { TEST: testVecArith }
- { TEST: testDotMul }
- { TEST: testVecLogic }
- { TEST: testComplex }
- { TEST: testCnt }
- { TEST: testVecRelat }
- { TEST: testShufflePack }
- { TEST: testMUL }
- { TEST: testHWLP }
- { TEST: testMacNorm }
- { TEST: testDivRem }
- { TEST: testVariadic }
- { TEST: testMAC }
- { TEST: testLoadStore }
- { TEST: testALUExt }
- { TEST: testBuiltins }
script:
- echo "Running ml tests"
- source sw/pulp-runtime/configs/pulpissimo.sh
- echo "Running riscv tests"
- source sw/pulp-runtime/configs/pulpissimo_cv32.sh
- export VSIM_PATH=$PWD/build/questasim
- cd sw/regression_tests/riscv_tests && plptest --threads 32 --stdout
- echo "Generating junit test results"
- /usr/sepp/bin/python3.4 -m junit2htmlreport junit-reports/TEST-*.xml
artifacts:
name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
paths:
- sw/regression_tests/riscv_tests/junit-reports/TEST-*.html
- sw/regression_tests/riscv_tests/junit-reports/TEST-*.xml
reports:
junit: sw/regression_tests/riscv_tests/junit-reports/TEST-*.xml
- cd sw/regression_tests/riscv_tests/${TEST}
- make clean all run

freertos_helloworld:
stage: test
Expand All @@ -150,7 +191,7 @@ freertos_helloworld:
- cd sw/pulp-freertos
- source env/pulpissimo-cv32e40p.sh
- cd tests/hello_world_pmsis
- make all run
- $QUESTA make all run

test_dm:
stage: test
Expand All @@ -173,21 +214,21 @@ fpga_synth_genesys2:
artifacts:
name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
paths:
- fpga/pulpissimo_genesys2.bit
- fpga/pulpissimo_genesys2.bin
- fpga/*.jou
- fpga/*.log
- fpga/*.str
- fpga/pulpissimo-genesys2/reports
- fpga/pulpissimo-genesys2/rtl
- fpga/pulpissimo-genesys2/tcl
- fpga/pulpissimo-genesys2/pulpissimo_genesys2.xpr
- fpga/pulpissimo-genesys2/fpga-settings.mk
- fpga/pulpissimo-genesys2/*.log
- fpga/pulpissimo-genesys2/*.cfg
- fpga/pulpissimo-genesys2/*.gdb
- fpga/pulpissimo-genesys2/*.jou
- fpga/pulpissimo-genesys2/*.log
- target/fpga/pulpissimo_genesys2.bit
- target/fpga/pulpissimo_genesys2.bin
- target/fpga/*.jou
- target/fpga/*.log
- target/fpga/*.str
- target/fpga/pulpissimo-genesys2/reports
- target/fpga/pulpissimo-genesys2/rtl
- target/fpga/pulpissimo-genesys2/tcl
- target/fpga/pulpissimo-genesys2/pulpissimo_genesys2.xpr
- target/fpga/pulpissimo-genesys2/fpga-settings.mk
- target/fpga/pulpissimo-genesys2/*.log
- target/fpga/pulpissimo-genesys2/*.cfg
- target/fpga/pulpissimo-genesys2/*.gdb
- target/fpga/pulpissimo-genesys2/*.jou
- target/fpga/pulpissimo-genesys2/*.log

fpga_synth_nexys_video:
stage: test
Expand All @@ -198,21 +239,21 @@ fpga_synth_nexys_video:
artifacts:
name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
paths:
- fpga/pulpissimo_nexys_video.bit
- fpga/pulpissimo_nexys_video.bin
- fpga/*.jou
- fpga/*.log
- fpga/*.str
- fpga/pulpissimo-nexys_video/reports
- fpga/pulpissimo-nexys_video/rtl
- fpga/pulpissimo-nexys_video/tcl
- fpga/pulpissimo-nexys_video/pulpissimo_nexys_video.xpr
- fpga/pulpissimo-nexys_video/fpga-settings.mk
- fpga/pulpissimo-nexys_video/*.log
- fpga/pulpissimo-nexys_video/*.cfg
- fpga/pulpissimo-nexys_video/*.gdb
- fpga/pulpissimo-nexys_video/*.jou
- fpga/pulpissimo-nexys_video/*.log
- target/fpga/pulpissimo_nexys_video.bit
- target/fpga/pulpissimo_nexys_video.bin
- target/fpga/*.jou
- target/fpga/*.log
- target/fpga/*.str
- target/fpga/pulpissimo-nexys_video/reports
- target/fpga/pulpissimo-nexys_video/rtl
- target/fpga/pulpissimo-nexys_video/tcl
- target/fpga/pulpissimo-nexys_video/pulpissimo_nexys_video.xpr
- target/fpga/pulpissimo-nexys_video/fpga-settings.mk
- target/fpga/pulpissimo-nexys_video/*.log
- target/fpga/pulpissimo-nexys_video/*.cfg
- target/fpga/pulpissimo-nexys_video/*.gdb
- target/fpga/pulpissimo-nexys_video/*.jou
- target/fpga/pulpissimo-nexys_video/*.log

fpga_synth_nexys:
stage: test
Expand All @@ -223,23 +264,23 @@ fpga_synth_nexys:
artifacts:
name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
paths:
- fpga/pulpissimo_nexys.bit
- fpga/pulpissimo_nexys.bin
- fpga/*.jou
- fpga/*.log
- fpga/*.str
- fpga/pulpissimo-nexys/reports
- fpga/pulpissimo-nexys/rtl
- fpga/pulpissimo-nexys/tcl
- fpga/pulpissimo-nexys/pulpissimo_nexys.xpr
- fpga/pulpissimo-nexys/fpga-settings.mk
- fpga/pulpissimo-nexys/*.log
- fpga/pulpissimo-nexys/*.cfg
- fpga/pulpissimo-nexys/*.gdb
- fpga/pulpissimo-nexys/*.jou
- fpga/pulpissimo-nexys/*.log
- target/fpga/pulpissimo_nexys.bit
- target/fpga/pulpissimo_nexys.bin
- target/fpga/*.jou
- target/fpga/*.log
- target/fpga/*.str
- target/fpga/pulpissimo-nexys/reports
- target/fpga/pulpissimo-nexys/rtl
- target/fpga/pulpissimo-nexys/tcl
- target/fpga/pulpissimo-nexys/pulpissimo_nexys.xpr
- target/fpga/pulpissimo-nexys/fpga-settings.mk
- target/fpga/pulpissimo-nexys/*.log
- target/fpga/pulpissimo-nexys/*.cfg
- target/fpga/pulpissimo-nexys/*.gdb
- target/fpga/pulpissimo-nexys/*.jou
- target/fpga/pulpissimo-nexys/*.log

fpga_synth_nexys_zcu104:
fpga_synth_zcu104:
stage: test
before_script:
script:
Expand All @@ -248,21 +289,21 @@ fpga_synth_nexys_zcu104:
artifacts:
name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
paths:
- fpga/pulpissimo_zcu104.bit
- fpga/pulpissimo_zcu104.bin
- fpga/*.jou
- fpga/*.log
- fpga/*.str
- fpga/pulpissimo-zcu104/reports
- fpga/pulpissimo-zcu104/rtl
- fpga/pulpissimo-zcu104/tcl
- fpga/pulpissimo-zcu104/pulpissimo_zcu104.xpr
- fpga/pulpissimo-zcu104/fpga-settings.mk
- fpga/pulpissimo-zcu104/*.log
- fpga/pulpissimo-zcu104/*.cfg
- fpga/pulpissimo-zcu104/*.gdb
- fpga/pulpissimo-zcu104/*.jou
- fpga/pulpissimo-zcu104/*.log
- target/fpga/pulpissimo_zcu104.bit
- target/fpga/pulpissimo_zcu104.bin
- target/fpga/*.jou
- target/fpga/*.log
- target/fpga/*.str
- target/fpga/pulpissimo-zcu104/reports
- target/fpga/pulpissimo-zcu104/rtl
- target/fpga/pulpissimo-zcu104/tcl
- target/fpga/pulpissimo-zcu104/pulpissimo_zcu104.xpr
- target/fpga/pulpissimo-zcu104/fpga-settings.mk
- target/fpga/pulpissimo-zcu104/*.log
- target/fpga/pulpissimo-zcu104/*.cfg
- target/fpga/pulpissimo-zcu104/*.gdb
- target/fpga/pulpissimo-zcu104/*.jou
- target/fpga/pulpissimo-zcu104/*.log

fpga_synth_zcu102:
stage: test
Expand All @@ -273,21 +314,21 @@ fpga_synth_zcu102:
artifacts:
name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
paths:
- fpga/pulpissimo_zcu102.bit
- fpga/pulpissimo_zcu102.bin
- fpga/*.jou
- fpga/*.log
- fpga/*.str
- fpga/pulpissimo-zcu102/reports
- fpga/pulpissimo-zcu102/rtl
- fpga/pulpissimo-zcu102/tcl
- fpga/pulpissimo-zcu102/pulpissimo_zcu102.xpr
- fpga/pulpissimo-zcu102/fpga-settings.mk
- fpga/pulpissimo-zcu102/*.log
- fpga/pulpissimo-zcu102/*.cfg
- fpga/pulpissimo-zcu102/*.gdb
- fpga/pulpissimo-zcu102/*.jou
- fpga/pulpissimo-zcu102/*.log
- target/fpga/pulpissimo_zcu102.bit
- target/fpga/pulpissimo_zcu102.bin
- target/fpga/*.jou
- target/fpga/*.log
- target/fpga/*.str
- target/fpga/pulpissimo-zcu102/reports
- target/fpga/pulpissimo-zcu102/rtl
- target/fpga/pulpissimo-zcu102/tcl
- target/fpga/pulpissimo-zcu102/pulpissimo_zcu102.xpr
- target/fpga/pulpissimo-zcu102/fpga-settings.mk
- target/fpga/pulpissimo-zcu102/*.log
- target/fpga/pulpissimo-zcu102/*.cfg
- target/fpga/pulpissimo-zcu102/*.gdb
- target/fpga/pulpissimo-zcu102/*.jou
- target/fpga/pulpissimo-zcu102/*.log

sim_questa_multivers:
stage: sim_questa_multivers
Expand Down Expand Up @@ -340,7 +381,6 @@ spi_boot:
- printf "#include <stdio.h>\nint main(){\n printf(\"Hello World\\\n\");\n return 0;\n}\n" > hello/hello.c
- printf "PULP_APP = hello\nPULP_APP_FC_SRCS = hello.c\nPULP_APP_HOST_SRCS = hello.c\nPULP_CFLAGS = -O3 -g\n\ninclude \$(PULP_SDK_HOME)/install/rules/pulp_rt.mk\n" > hello/Makefile
script:
- make scripts-bender-vsim-vips all
- export VSIM_PATH=$PWD/build/questasim
- source pulp-runtime/configs/pulpissimo_cv32.sh
- make -C hello clean all run bootmode=spi PULP_RUNTIME_GCC_TOOLCHAIN=/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0
- make -C hello clean all run bootmode=spi
2 changes: 1 addition & 1 deletion sw/pulp-runtime
Submodule pulp-runtime updated 1 files
+1 −1 scripts/bwruntests.py
10 changes: 7 additions & 3 deletions target/sim/questasim/Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -58,16 +58,20 @@ else
cd $(QUESTA_BUILD_DIR) && $(VSIM_BIN) $(VSIM_ARGS) -gui -do "vsim +BINARY_SREC_PATH='$< $(SIM_TOP_OPT)"
endif

.PHONY: relink
relink:
@mkdir -p $(QUESTA_BUILD_DIR)
@ln -snf $(PULPISSIMO_ROOT)/target/sim/questasim/waves $(QUESTA_BUILD_DIR)/waves
@ln -snf $(PULPISSIMO_ROOT)/target/sim/questasim/tcl_files $(QUESTA_BUILD_DIR)/tcl_files

## (Re)Compile PULPissimo using Questasim.
## @param VSIM_BIN=vsim The command to invoke vsim. Default: 'vsim'
## @param VSIM_ARGS='-64' Additional args to supply to vsim during tool invocation
## @param SIM_TOP='tb_pulp' The toplevel module to optimize for simulation. Default: tb_pulp
.PHONY: build
build: $(QUESTA_BUILD_DIR)/compile.tcl
build: $(QUESTA_BUILD_DIR)/compile.tcl relink
cd $(QUESTA_BUILD_DIR) && $(VSIM_BIN) $(VSIM_ARGS) -c -do 'source compile.tcl; quit'
cd $(QUESTA_BUILD_DIR) && $(VSIM_BIN) $(VSIM_ARGS) -c -do 'vopt $(VOPT_ARGS) -o $(SIM_TOP_OPT) $(SIM_TOP) -work work; quit'
@ln -snf $(PULPISSIMO_ROOT)/target/sim/questasim/waves $(QUESTA_BUILD_DIR)/waves
@ln -snf $(PULPISSIMO_ROOT)/target/sim/questasim/tcl_files $(QUESTA_BUILD_DIR)/tcl_files
@echo "Finished building design $(SIM_TOP). The optimized design has been stored in a unit called '$(SIM_TOP_OPT)'."
ifneq ($(VSIM_PATH), $(PULPISSIMO_ROOT)/build/questasim)
@echo ""
Expand Down

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