Add verilator simulation

simulation/include

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+../include/

simulation/verilator/Makefile

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+verilator: toplevel_sim.v required_modules.txt simulator.cpp
+	verilator -Wno-fatal --cc toplevel_sim.v -f required_modules.txt --exe simulator.cpp
+	cp obj_dir/* .
+	make -f Vtoplevel_sim.mk
+	rm -f *.o *.d Vtoplevel_sim_* Vtoplevel_sim.*
+	rm -r obj_dir
+	#
+	# To run the verilated simulation, type ./Vtoplevel_sim
+	#

simulation/verilator/required_modules.txt

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+verilog/CSR.v
+verilog/adder.v
+verilog/alu.v
+verilog/alu_control.v
+verilog/branch_decide.v
+verilog/branch_predictor.v
+verilog/control_unit.v
+verilog/cpu.v
+verilog/dataMem_mask_gen.v
+verilog/data_mem.v
+verilog/forwarding_unit.v
+verilog/imm_gen.v
+verilog/instruction_mem.v
+verilog/mux2to1.v
+verilog/pipeline_registers.v
+verilog/program_counter.v
+verilog/register_file.v

simulation/verilator/simulator.cpp

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+#include <stdio.h>
+#include <verilated.h>
+#include "Vtoplevel_sim.h"
+
+vluint64_t vtime = 0;
+bool clk = false;
+int led = 255;
+
+int main(int argc, char** argv, char** env)
+{
+	// Initialise Verilator
+	Verilated::commandArgs(argc, argv);
+	// Create a new instance of the Verilated module
+	Vtoplevel_sim* top = new Vtoplevel_sim;
+
+	while (!Verilated::gotFinish())
+	{
+		// Toggle the clock
+		clk = not clk;
+		top->clk = int(clk);
+
+		top->eval();
+
+		// If the LED has changed, print its new value
+		if (led != int(top->led))
+		{
+			led = int(top->led);
+			printf("%i\n", led);
+		}
+		vtime++;
+	}
+
+        delete top;
+        exit(0);
+}

simulation/verilator/toplevel_sim.v

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+/*
+	Authored 2018-2019, Ryan Voo.
+	Modified 2021, Theo Brown
+
+	All rights reserved.
+	Redistribution and use in source and binary forms, with or without
+	modification, are permitted provided that the following conditions
+	are met:
+
+	*	Redistributions of source code must retain the above
+		copyright notice, this list of conditions and the following
+		disclaimer.
+
+	*	Redistributions in binary form must reproduce the above
+		copyright notice, this list of conditions and the following
+		disclaimer in the documentation and/or other materials
+		provided with the distribution.
+
+	*	Neither the name of the author nor the names of its
+		contributors may be used to endorse or promote products
+		derived from this software without specific prior written
+		permission.
+
+	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+	"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+	LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+	FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+	COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+	INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+	BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+	LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+	CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+	LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+	ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+	POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+/*
+ *	top.v
+ *
+ *	Top level entity, linking cpu with data and instruction memory.
+ *	This version is modified to use an external clock, provided for example by Verilator
+ */
+
+module top (input clk, output [7:0] led);
+	wire		clk_proc;
+	wire		data_clk_stall;
+
+	/*
+	 *	Memory interface
+	 */
+	wire[31:0]	inst_in;
+	wire[31:0]	inst_out;
+	wire[31:0]	data_out;
+	wire[31:0]	data_addr;
+	wire[31:0]	data_WrData;
+	wire		data_memwrite;
+	wire		data_memread;
+	wire[3:0]	data_sign_mask;
+
+
+	cpu processor(
+		.clk(clk_proc),
+		.inst_mem_in(inst_in),
+		.inst_mem_out(inst_out),
+		.data_mem_out(data_out),
+		.data_mem_addr(data_addr),
+		.data_mem_WrData(data_WrData),
+		.data_mem_memwrite(data_memwrite),
+		.data_mem_memread(data_memread),
+		.data_mem_sign_mask(data_sign_mask)
+	);
+
+	instruction_memory inst_mem( 
+		.addr(inst_in), 
+		.out(inst_out)
+	);
+
+	data_mem data_mem_inst(
+			.clk(clk),
+			.addr(data_addr),
+			.write_data(data_WrData),
+			.memwrite(data_memwrite), 
+			.memread(data_memread), 
+			.read_data(data_out),
+			.sign_mask(data_sign_mask),
+			.led(led),
+			.clk_stall(data_clk_stall)
+		);
+
+	assign clk_proc = (data_clk_stall) ? 1'b1 : clk;
+endmodule

simulation/verilator/verilog

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+../../verilog/