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Public- Design and implementation of a 32-bit RISC-V processor supporting the RV32IM instruction set, developed as part of the Advanced Computer Architecture course (CO502). Webpage: https://cepdnaclk.github.io/e20-co502-RV32IM_Pipelined_Processor
portal.ce.pdn.ac.lk
Public- P-E-BO Desk Companion is an intelligent, interactive robot assistant designed to help with daily tasks and home automation. By integrating IoT, voice recognition, and face recognition, PE-BO adapts to the user's environment, maximizing convenience and interactivity.
SimpleEq
Public- Smart canteen management system is a system designed to increase the efficiency of cafeterias in different working environments and to provide more user friendly functions such as smart pay, an app to keep track of user activities, digital touch screen for the menu item selection,congestion alert system.
e19-co326-air-quality-management-system
Public templatecepdnaclk.github.io
PublicGithub pages website for Department of Computer Engineering, University of Peradeniya. https://cepdnaclk.github.io- This Smart IoT Lighting System is designed for indoor lighting, integrating hardware with cloud connectivity for seamless control. Users can conveniently configure preferences and manage settings via a secure mobile app with voice command support, ensuring personalized and efficient lighting experiences, ease of use, and robust data security.
url.ce.pdn.ac.lk
PublicThis repository can be used to generate shorten URLs, with the prefix https://url.ce.pdn.ac.lke20-3yp-OceanEyes
Public- The Cathlab Management System modernizes Peradeniya Hospital's catheterization lab by replacing manual processes with a digital platform. It centralizes patient data, automates workflows, and improves efficiency, accuracy, and scalability, enabling better care for cardiovascular patients.
e20-3yp-Smart-Aquarium
Public- This Git repository contains the implementation of a RISC32IM processor pipeline using Verilog. The pipeline includes stages for instruction fetch, decode, execute, memory access, and write-back. The implementation includes a testbench for verification.
- The RV32IM pipeline processor project designs a 32-bit RISC-V processor with 5 stages: IF, ID, EX, MEM, WB. It supports RV32I base and M-extension (MUL/DIV), using forwarding, stalling, and branch prediction to manage hazards. Implemented in Verilog, it is simulated, tested with RISC-V tools, and optimized for performance.
e20-co227-MONA-Dashboard
PublicOur project involves creating an advanced real-time monitoring dashboard for production environments. This dashboard enhances efficiency and reliability with critical insights and timely alerts. Designed for user-friendliness, it ensures operators and managers can easily access and interpret the data needed for optimal production performance.fieldselection
Publice20-co543-SkinVision
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