Announcing a tool to generate VHDL registers (+ more)

[mbuechl]

Hi all,

We (an FPGA firmware team at DESY [1]) made a tool based on systemrdl-compiler. It generates VHDL (and more) based on templates, a bit similar to PeakRDL-verilog, but using our own weird template engine instead of Jinja2. I just uploaded it on PyPI [2] and I thought that was a good time to announce it somehow, and say thank you to @amykyta3 and all contributors. SystemRDL Compiler is great!

You might have seen HECTARE [3] by @j-marjanovic who was working at a different team here at DESY. It wasn't enough for our purpose so we took the idea and made a new thing. It handles arrays of registers, for example. It also generates record types so that you can use node instances by their instance names within VHDL, similar to PeakRDL-regblock [4] I think. And because the template engine and the generated context don't care about the language, we can also generate AsciiDoc documentation or C headers by just writing new templates.

It still has many limitations, e.g. it is limited to AXI4-Lite, doesn't know about interrupts, and the register+field implementation is far from complete, but we want to gradually improve and extend it. Also there is an obvious lack of (publishable) documentation, and the generation of context for the template engine is a bit of a mess.

We made this because we wanted to replace our existing register generation workflow. It had to fit into our custom FPGA build environment [5] and the existing software interface, with its multiple levels of hierarchy, each having a combination of registers and external components (e.g. memories or other addrmap). As a result this probably doesn't fit into the PeakRDL concept - we called it DesyRDL. We still hope that this will be useful to others in some way. Also we're new to sharing with the free & open source community and haven't set up any issue tracker or anything yet, we just use this Gitlab instance [6]. But we will be happy to hear your comments and suggestions!

Michael

[1] https://msk.desy.de/
[2] https://pypi.org/project/desyrdl/0.2.0/
[3] https://github.com/MicroTCA-Tech-Lab/hectare
[4] https://peakrdl-regblock.readthedocs.io/en/latest/hwif.html
[5] https://fpgafw.pages.desy.de/docs-pub/fwk/index.html
[6] https://gitlab.desy.de/fpgafw/tools/desyrdl

[amykyta3]

@mbuechl This is great!
Would you be interested in extending DesyRDL to register itself as a plugin to the PeakRDL command line tool?
I have instructions on how to do this here: https://peakrdl.readthedocs.io/en/latest/for-devs/exporter-plugin.html
I would be happy to draft up a merge request to implement this.

[mbuechl]

Cool, I had seen the placeholder for this tool a long time ago. Having DesyRDL as a plugin sounds like a good idea, and it looks easy. Basically it would be an alternative to DesyRDL's desyrdl/desyrdl.py, right?
I will be on vacation in the coming week. If you draft a merge request in the meantime then that's great, although we currently host the code on gitlab.desy.de where you cannot login, so you can't collaborate there, which is lame. We do consider moving our code to Gitlab or Github. Until then - a fork on Github, maybe? Otherwise I'll give it a try after my vacation.