licensing: use one line SPDX format in each file

openrisc · Jan 9, 2022 · c666fde · c666fde
1 parent 6bc5bca
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diff --git a/bench/formal/Makefile b/bench/formal/Makefile
@@ -1,12 +1,5 @@
 ###########################################################
-# This source describes Open Hardware and is licensed under the CERN-OHLW v2
-#
-# You may redistribute and modify this documentation and make products
-# using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-# This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-# WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-# AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-# for applicable conditions.
+# SPDX-License-Identifier: CERN-OHL-W-2.0
 #
 # Description: Simplistic makefile for running formal tests
 #

diff --git a/bench/formal/f_multiclock_op.v b/bench/formal/f_multiclock_op.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx formal multiclock alu operation checker
 

diff --git a/bench/formal/fspr_master.v b/bench/formal/fspr_master.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
   ***************************************************************************** */
 
  module fspr_master

diff --git a/bench/formal/fspr_slave.v b/bench/formal/fspr_slave.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
   ***************************************************************************** */
 
 module fspr_slave

diff --git a/bench/verilog/mor1kx_monitor.v b/bench/verilog/mor1kx_monitor.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx monitor module
  

diff --git a/bench/verilog/mor1kx_traceport_monitor.v b/bench/verilog/mor1kx_traceport_monitor.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 ***************************************************************************** */
 
 `include "mor1kx-defines.v"

diff --git a/rtl/verilog/mor1kx-defines.v b/rtl/verilog/mor1kx-defines.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx defines
 

diff --git a/rtl/verilog/mor1kx-sprs.v b/rtl/verilog/mor1kx-sprs.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: SPR definitions
 

diff --git a/rtl/verilog/mor1kx.v b/rtl/verilog/mor1kx.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx processor top level
 

diff --git a/rtl/verilog/mor1kx_branch_prediction.v b/rtl/verilog/mor1kx_branch_prediction.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: Branch prediction module
   Generates a predicted flag output and compares that to the real flag

diff --git a/rtl/verilog/mor1kx_branch_predictor_gshare.v b/rtl/verilog/mor1kx_branch_predictor_gshare.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: gshare branch predictor
   This predictor is based on array of FSMs with 4 states: strongly not taken,

diff --git a/rtl/verilog/mor1kx_branch_predictor_saturation_counter.v b/rtl/verilog/mor1kx_branch_predictor_saturation_counter.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: Saturating counter branch predictor
   This is FSM with 4 states: strongly not taken, weakly not taken,

diff --git a/rtl/verilog/mor1kx_branch_predictor_simple.v b/rtl/verilog/mor1kx_branch_predictor_simple.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: Simple branch predictor implementation
   We assume flag to be "true" if instruction is bf and it jumps backwords

diff --git a/rtl/verilog/mor1kx_bus_if_wb32.v b/rtl/verilog/mor1kx_bus_if_wb32.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx processor Wishbone bus bridge
 

diff --git a/rtl/verilog/mor1kx_cache_lru.v b/rtl/verilog/mor1kx_cache_lru.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: Data cache LRU implementation
 

diff --git a/rtl/verilog/mor1kx_cfgrs.v b/rtl/verilog/mor1kx_cfgrs.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx SPRs indicating configuration and version
 

diff --git a/rtl/verilog/mor1kx_cpu.v b/rtl/verilog/mor1kx_cpu.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: CPU wrapper module
 

diff --git a/rtl/verilog/mor1kx_cpu_cappuccino.v b/rtl/verilog/mor1kx_cpu_cappuccino.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: "Cappuccino" pipeline CPU module
 

diff --git a/rtl/verilog/mor1kx_cpu_espresso.v b/rtl/verilog/mor1kx_cpu_espresso.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: Espresso pipeline CPU module
 

diff --git a/rtl/verilog/mor1kx_cpu_prontoespresso.v b/rtl/verilog/mor1kx_cpu_prontoespresso.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: "Pronto espresso" pipeline CPU module
 

diff --git a/rtl/verilog/mor1kx_ctrl_cappuccino.v b/rtl/verilog/mor1kx_ctrl_cappuccino.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx control unit
 

diff --git a/rtl/verilog/mor1kx_ctrl_espresso.v b/rtl/verilog/mor1kx_ctrl_espresso.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx espresso pipeline control unit
 

diff --git a/rtl/verilog/mor1kx_ctrl_prontoespresso.v b/rtl/verilog/mor1kx_ctrl_prontoespresso.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx pronto espresso pipeline control unit
 

diff --git a/rtl/verilog/mor1kx_dcache.v b/rtl/verilog/mor1kx_dcache.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: Data cache implementation
 

diff --git a/rtl/verilog/mor1kx_decode.v b/rtl/verilog/mor1kx_decode.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx decode unit
 

diff --git a/rtl/verilog/mor1kx_decode_execute_cappuccino.v b/rtl/verilog/mor1kx_decode_execute_cappuccino.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: Cappuccino decode to execute module.
   - Decode to execute stage signal passing.

diff --git a/rtl/verilog/mor1kx_dmmu.v b/rtl/verilog/mor1kx_dmmu.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: Data MMU implementation
 

diff --git a/rtl/verilog/mor1kx_execute_alu.v b/rtl/verilog/mor1kx_execute_alu.v
@@ -1,12 +1,5 @@
 /* ****************************************************************************
-  This source describes Open Hardware and is licensed under the CERN-OHLW v2
-
-  You may redistribute and modify this documentation and make products
-  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
-  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
-  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
-  for applicable conditions.
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx execute stage ALU