mriscv_vivado

The micro controller also was tested under a NEXYS4 FPGA platform. The whole system is composed by two masters (SPI and mriscv core) and 8 slaves. All the peripherals are communicated with the masters through a AXI4-lite bus. The slaves are a block that emulates the processor RAM, a DDR2 driver, a ROM with a built-in SPI protocol, a GPIO with RS232 support, a SPI, a DAC, a 7-segment display and xADC. xADC is an interface to the ADCs available in the FPGA. The file "diagram.pdf" shows the block diagram of the implemented micro controller.