samples: benchmark: coremark: add FLPR support for nRF54L15 DK #20462

kapi-no · 2025-02-18T14:13:06Z

Added the FLPR core support for the nRF54L15 DK board target in the CoreMark sample.

Ref: NCSDK-30327

NordicBuilder · 2025-02-18T14:16:40Z

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Build number: 8

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sdk-nrf: PR head: 5f1b98b0502e55a4730978dff1195d1feeabdd69

more details

sdk-nrf:

PR head: 5f1b98b0502e55a4730978dff1195d1feeabdd69
merge base: cbeb54f710176f373585e10aafc8bf8c64582031
target head (main): 2ad79c602d973ecfd471103e14d5f7e3e2a993a2
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Github labels

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List of changed files detected by CI (8)

doc
│  ├── nrf
│  │  ├── releases_and_maturity
│  │  │  ├── releases
│  │  │  │  │ release-notes-changelog.rst
samples
│  ├── benchmarks
│  │  ├── coremark
│  │  │  ├── Kconfig
│  │  │  ├── Kconfig.sysbuild
│  │  │  ├── README.rst
│  │  │  ├── boards
│  │  │  │  ├── nrf54l15dk_nrf54l15_cpuapp.overlay
│  │  │  │  ├── nrf54l15dk_nrf54l15_cpuflpr.conf
│  │  │  │  │ nrf54l15dk_nrf54l15_cpuflpr.overlay
│  │  │  │ sysbuild.cmake

Outputs:

Toolchain

Version: aedb4c0245
Build docker image: docker-dtr.nordicsemi.no/sw-production/ncs-build:aedb4c0245_bece0367df

Test Spec & Results: ✅ Success; ❌ Failure; 🟠 Queued; 🟡 Progress; ◻️ Skipped; ⚠️ Quarantine

◻️ Toolchain - Skipped: existing toolchain is used
✅ Build twister
- sdk-nrf test count: 41
✅ Integration tests

Disabled integration tests

- desktop52_verification
- doc-internal
- test_ble_nrf_config
- test-fw-nrfconnect-apps
- test-fw-nrfconnect-ble_mesh
- test-fw-nrfconnect-ble_samples
- test-fw-nrfconnect-boot
- test-fw-nrfconnect-chip
- test-fw-nrfconnect-fem
- test-fw-nrfconnect-nfc
- test-fw-nrfconnect-nrf-iot_cloud
- test-fw-nrfconnect-nrf-iot_libmodem-nrf
- test-fw-nrfconnect-nrf-iot_lwm2m
- test-fw-nrfconnect-nrf-iot_mosh
- test-fw-nrfconnect-nrf-iot_positioning
- test-fw-nrfconnect-nrf-iot_samples
- test-fw-nrfconnect-nrf-iot_serial_lte_modem
- test-fw-nrfconnect-nrf-iot_thingy91
- test-fw-nrfconnect-nrf-iot_zephyr_lwm2m
- test-fw-nrfconnect-nrf_crypto
- test-fw-nrfconnect-proprietary_esb
- test-fw-nrfconnect-ps
- test-fw-nrfconnect-rpc
- test-fw-nrfconnect-rs
- test-fw-nrfconnect-tfm
- test-fw-nrfconnect-thread
- test-fw-nrfconnect-zigbee
- test-low-level
- test-sdk-audio
- test-sdk-dfu
- test-sdk-find-my
- test-sdk-mcuboot
- test-sdk-pmic-samples
- test-sdk-sidewalk
- test-sdk-wifi
- test-secdom-samples-public

Note: This message is automatically posted and updated by the CI

NordicBuilder · 2025-02-18T14:32:50Z

You can find the documentation preview for this PR at this link.

Note: This comment is automatically posted by the Documentation Publish GitHub Action.

samples/benchmarks/coremark/Kconfig.sysbuild

mkapala-nordic · 2025-02-20T11:10:26Z

samples/benchmarks/coremark/Kconfig

-		!(SOC_NRF54H20_CPUPPR)
+config APP_BUTTON_AND_LED_UNSUPPORTED
+	bool
 	default y if SOC_NRF54H20_CPUPPR
+	default y if SOC_NRF54L05_CPUFLPR
+	default y if SOC_NRF54L10_CPUFLPR
+	default y if SOC_NRF54L15_CPUFLPR


consider: please add help why it is not supported if possible

I added a comment for the nRF54H20 DK as it seems that one button on the nRF54L15 DK is assigned to a different GPIO port. Thanks to that, I managed to have a different button assigned for the App core (Button 0) and a different button assigned for the FLPR core (Button 3).

github-actions · 2025-02-20T12:37:48Z

After documentation is built, you will find the preview for this PR here.

Preview links for modified nRF Connect SDK documents:

MarekPieta · 2025-02-20T14:26:43Z

samples/benchmarks/coremark/Kconfig.sysbuild

@@ -6,6 +6,11 @@

 source "share/sysbuild/Kconfig"

+config APP_CPUFLPR_RUN
+	bool "Run the CoreMark benchmark on the FLPR core"
+	depends on SUPPORT_FLPRCORE && !SOC_NRF54H20_CPUAPP && !SOC_NRF54L05_CPUAPP && !SOC_NRF54L10_CPUAPP


I think that SB_CONFIG_SUPPORT_FLPRCORE should not be enabled for L05 and L10 (as FLPR is currently unsupported for these SoCs in our SDK). We overlooked that during our previous review.

Consider explicitly mentioning in Kconfig help that CoreMark does not support FLPR for nRF54H20 SoC yet

MarekPieta · 2025-02-20T14:30:29Z

samples/benchmarks/coremark/README.rst

@@ -171,8 +193,22 @@ CONFIG_APP_MODE_FLASH_AND_RUN - Start CoreMark sample automatically after flashi
   Otherwise, it will wait for the button press.

 .. note::
-   The :kconfig:option:`CONFIG_APP_MODE_FLASH_AND_RUN` Kconfig option is always enabled for the PPR core.
-   This core does not use buttons.
+   The :kconfig:option:`CONFIG_APP_MODE_FLASH_AND_RUN` Kconfig option is always enabled for the PPR and FLPR cores on the ``nrf54h20dk/nrf54h20/cpuapp`` board target.


Should we already mention FLPR on nRF54H? It seems not yet supported by the sample

you are right. Let's modify this in a subsequent PR

MarekPieta · 2025-02-21T06:53:40Z

samples/benchmarks/coremark/Kconfig

-	bool "Run CoreMark benchmark on start up" if \
-		!(SOC_NRF54H20_CPUPPR)
+config APP_BUTTON_AND_LED_UNSUPPORTED
+	bool


Can we get the default relying on button and led DT aliases? Maybe e.g. $(dt_alias_enabled,<node alias>) could be used here?

I would also call it APP_BUTTON_AND_LED_SUPPORTED (to avoid double negation later)

MarekPieta · 2025-02-21T06:57:56Z

samples/benchmarks/coremark/README.rst

-   .. group-tab:: nRF52 and nRF53 DKs
+   .. group-tab:: nRF52 DKs
+
+      Button 1:


Maybe we could avoid duplicating information from the introduction sentence)? E.g.:

.. group-tab:: nRF52 DKs Application core: ``Button 1`` and ``LED 1``

I would need to get some feedback from our technical writers as your suggestion changes the template for documenting UI interface

@peknis? Any thoughts regarding @MarekPieta suggestion?

Why not, as the essential is said already in the introduction. However, have the button and LED in bold.

MarekPieta · 2025-02-21T07:04:42Z

samples/benchmarks/coremark/boards/nrf54l15dk_nrf54l15_cpuapp.overlay

+	status = "reserved";
+};
+
+/* Reserve button and LED related resources for the FLPR core. */


LED3 uses GPIO1 port which is actually not reserved here

I would remove the reservation syntax. We should just be careful to avoid using the same HW peripherals from two different cores.

MarekPieta · 2025-02-21T07:05:02Z

samples/benchmarks/coremark/boards/nrf54l15dk_nrf54l15_cpuapp.overlay

+ #include "app_aliases_common.overlay"
+
+/* The following configuration is required to run the CPUFLPR core.
+ * It is imported from the nordic-flpr snippet.


Can we simply use the snippet from Zephyr and avoid copying file content here?
Ref: https://docs.zephyrproject.org/latest/build/snippets/using.html#application-required-snippets

It would need a significant refactor also for the STM and the PPR snippet. Please create a task and we can improve this in the future. However, we would have a big if else block to cover each snippet variant for each board target

I am also trying to remove code duplications (1000lines+) using the Fast PAir Advertising Manager - it would be great to go back and help me remove this duplication is much more costly to maintain.

MarekPieta · 2025-02-21T07:15:18Z

samples/benchmarks/coremark/boards/nrf54l15dk_nrf54l15_cpuapp.overlay

+};
+
+/* Reserve button and LED related resources for the FLPR core. */
+&gpio0 {


Have you seen the dtc warnings during build?

CMake Warning at /home/mapi/ncs/zephyr/cmake/modules/dts.cmake:428 (message): dtc raised one or more warnings: /home/mapi/ncs/nrf/samples/benchmarks/coremark/build/coremark/zephyr/zephyr.dts:760.19-767.5: Warning (simple_bus_reg): /soc/reserved-memory: missing or empty reg/ranges property Call Stack (most recent call first): /home/mapi/ncs/zephyr/cmake/modules/zephyr_default.cmake:133 (include) /home/mapi/ncs/zephyr/share/zephyr-package/cmake/ZephyrConfig.cmake:66 (include) /home/mapi/ncs/zephyr/share/zephyr-package/cmake/ZephyrConfig.cmake:92 (include_boilerplate) CMakeLists.txt:8 (find_package)

Warning (simple_bus_reg): /soc/memory@2002f000: simple-bus unit address format error, expected "20028000" Call Stack (most recent call first): /home/mapi/ncs/zephyr/cmake/modules/zephyr_default.cmake:133 (include) /home/mapi/ncs/zephyr/share/zephyr-package/cmake/ZephyrConfig.cmake:66 (include) /home/mapi/ncs/zephyr/share/zephyr-package/cmake/ZephyrConfig.cmake:92 (include_boilerplate) CMakeLists.txt:8 (find_package)

May be worth to check what causes them

For some reason, building the sample locally fails for me (using Zephyr SDK 0.16.5). I will update my Zephyr SDK to 0.17.0 and recheck.

I have the same DTS warnings. They are caused by the nordic-flpr snippet configuration

Can we report them to the maintainers?

The CPUFLPR warning is actually caused by the following misaligned configuration between the following DTS files:

https://github.com/zephyrproject-rtos/zephyr/blob/main/dts/common/nordic/nrf54l15.dtsi#L17 (cpuflpr_sram: memory@2002f000)
https://github.com/zephyrproject-rtos/zephyr/blob/main/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.dts#L24
(reg = <0x20028000 DT_SIZE_K(96)>;)

MarekPieta · 2025-02-21T07:44:32Z

samples/benchmarks/coremark/README.rst

+.. _SB_CONFIG_APP_CPUFLPR_RUN:
+
+SB_CONFIG_APP_CPUFLPR_RUN - Enable execution for the FLPR core
+   Enable the benchmark execution also for the board targets with the FLPR core HW (for example, nRF54L15 and nRF54H20 SoCs).


Suggested change

Enable the benchmark execution also for the board targets with the FLPR core HW (for example, nRF54L15 and nRF54H20 SoCs).

Enable the benchmark execution also for the FLPR core for targets with the nRF54L15 SoC.

Current wording it misleading

this option does not cover only the nRF54L15, it will also be used to enable execution for nRF54H20 DK

rephrased the whole paragraph

MarekPieta · 2025-02-21T07:47:19Z

samples/benchmarks/coremark/README.rst

+
+   This option is not supported for the following board targets that include an SoC with the FLPR core:
+
+     * ``nrf54h20dk/nrf54h20/cpuapp``


Consider mentioning that nRF54H20 FLPR is not yet integrated in the sample, while L05 and L10 do not support FLPR at the SDK level

discussed offline, decided to not explain what is causing the lack of support for the listed board targets.

Added the FLPR core support for the nRF54L15 DK board target in the CoreMark sample. Ref: NCSDK-30327 Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>

kapi-no requested review from a team as code owners February 18, 2025 14:13

github-actions bot added the doc-required PR must not be merged without tech writer approval. label Feb 18, 2025

peknis approved these changes Feb 18, 2025

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mkapala-nordic reviewed Feb 20, 2025

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kapi-no force-pushed the coremark_flpr_support_nrf54l branch from b31f082 to 136595e Compare February 20, 2025 12:37

kapi-no force-pushed the coremark_flpr_support_nrf54l branch 5 times, most recently from f057a5e to f373765 Compare February 20, 2025 13:14

MarekPieta requested changes Feb 21, 2025

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samples: benchmark: coremark: add FLPR support for nRF54L15 DK

5f1b98b

Added the FLPR core support for the nRF54L15 DK board target in the CoreMark sample. Ref: NCSDK-30327 Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>

kapi-no force-pushed the coremark_flpr_support_nrf54l branch from f373765 to 5f1b98b Compare February 21, 2025 16:38

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	Enable the benchmark execution also for the board targets with the FLPR core HW (for example, nRF54L15 and nRF54H20 SoCs).
	Enable the benchmark execution also for the FLPR core for targets with the nRF54L15 SoC.


		This option is not supported for the following board targets that include an SoC with the FLPR core:

		* ``nrf54h20dk/nrf54h20/cpuapp``

samples: benchmark: coremark: add FLPR support for nRF54L15 DK #20462

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