samples: benchmark: coremark: add FLPR support for nRF54L15 DK

Added the FLPR core support for the nRF54L15 DK board target in the
CoreMark sample.

Ref: NCSDK-30327

Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>

doc/nrf/releases_and_maturity/releases/release-notes-changelog.rst

@@ -528,7 +528,10 @@ Other samples
 
 * :ref:`coremark_sample` sample:
 
-  * Added support for the nRF54L05 and nRF54L10 SoCs (emulated on nRF54L15 DK).
+  * Added:
+
+    * Support for the nRF54L05 and nRF54L10 SoCs (emulated on nRF54L15 DK).
+    * FLPR core support for the :ref:`zephyr:nrf54l15dk_nrf54l15` board target.
 
 Drivers
 =======

samples/benchmarks/coremark/Kconfig

@@ -6,10 +6,19 @@
 
 menu "CoreMark sample"
 
-config APP_MODE_FLASH_AND_RUN
-	bool "Run CoreMark benchmark on start up" if \
-		!(SOC_NRF54H20_CPUPPR)
+config APP_BUTTON_AND_LED_UNSUPPORTED
+	bool
 	default y if SOC_NRF54H20_CPUPPR
+	help
+	  The VPR cores do not have button and LED support on the nRF54H20 DK as GPIO pins
+	  connected to buttons and LEDs share the same GPIO port. The Zephyr framework does
+	  not support individual GPIO pin assignments. For instance, it is not possible to
+	  assign Button 0 to the application core and Button 2 to the FLPR core on
+	  the nRF54H20 DK as these buttons share the same GPIO port.
+
+config APP_MODE_FLASH_AND_RUN
+	bool "Run CoreMark benchmark on start up" if !APP_BUTTON_AND_LED_UNSUPPORTED
+	default y if APP_BUTTON_AND_LED_UNSUPPORTED
 	help
 	  If enabled, CoreMark will start execution immediately after the CPU starts up.
 	  It also disables LEDs and buttons.

samples/benchmarks/coremark/Kconfig.sysbuild

@@ -6,6 +6,11 @@
 
 source "share/sysbuild/Kconfig"
 
+config APP_CPUFLPR_RUN
+	bool "Run the CoreMark benchmark on the FLPR core"
+	depends on SUPPORT_FLPRCORE && !SOC_NRF54H20_CPUAPP && !SOC_NRF54L05_CPUAPP && !SOC_NRF54L10_CPUAPP
+	default y
+
 config APP_CPUNET_RUN
 	bool "Run the CoreMark benchmark on the network or radio core"
 	depends on SUPPORT_NETCORE

samples/benchmarks/coremark/README.rst

@@ -77,33 +77,55 @@ Each target CPU has an assigned button responsible for starting the benchmark an
 
 .. tabs::
 
-   .. group-tab:: nRF52 and nRF53 DKs
+   .. group-tab:: nRF52 DKs
+
+      Button 1:
+         Start the benchmark run on the application core.
+
+      LED 1:
+         Indicates ``test in progress`` on the application core.
+
+   .. group-tab:: nRF53 DKs
 
       Button 1:
          Start the benchmark run on the application core.
 
       Button 2:
-         Start the benchmark run on the network or radio core.
+         Start the benchmark run on the network core.
 
       LED 1:
          Indicates ``test in progress`` on the application core.
 
       LED 2:
-         Indicates ``test in progress`` on the network or radio core.
+         Indicates ``test in progress`` on the network core.
+
+   .. group-tab:: nRF54L DKs
+
+      Button 0:
+         Start the benchmark run on the application core.
 
-   .. group-tab:: nRF54 DKs
+      Button 3 (only supported for the ``nrf54l15dk/nrf54l15/cpuapp`` board target):
+         Start the benchmark run on the FLPR core.
+
+      LED 0:
+         Indicates ``test in progress`` on the application core.
+
+      LED 3 (only supported for the ``nrf54l15dk/nrf54l15/cpuapp`` board target):
+         Indicates ``test in progress`` on the FLPR core.
+
+   .. group-tab:: nRF54H DKs
 
       Button 0:
          Start the benchmark run on the application core.
 
       Button 1:
-         Start the benchmark run on the network or radio core.
+         Start the benchmark run on the radio core.
 
       LED 0:
          Indicates ``test in progress`` on the application core.
 
       LED 1:
-         Indicates ``test in progress`` on the network or radio core.
+         Indicates ``test in progress`` on the radio core.
 
 .. _coremark_configuration:
 
@@ -171,8 +193,22 @@ CONFIG_APP_MODE_FLASH_AND_RUN - Start CoreMark sample automatically after flashi
    Otherwise, it will wait for the button press.
 
 .. note::
-   The :kconfig:option:`CONFIG_APP_MODE_FLASH_AND_RUN` Kconfig option is always enabled for the PPR core.
-   This core does not use buttons.
+   The :kconfig:option:`CONFIG_APP_MODE_FLASH_AND_RUN` Kconfig option is always enabled for the PPR and FLPR cores.
+   These cores do not use buttons and LEDs.
+
+.. _SB_CONFIG_APP_CPUFLPR_RUN:
+
+SB_CONFIG_APP_CPUFLPR_RUN - Enable execution for the FLPR core
+   Enable the benchmark execution also for the FLPR core for the supported targets (for example, nRF54L15 and nRF54H20 SoCs).
+
+.. note::
+   FLPR code is run from RAM.
+
+   This option is not supported for the following board targets that include an SoC with the FLPR core:
+
+     * ``nrf54h20dk/nrf54h20/cpuapp``
+     * ``nrf54l15dk/nrf54l05/cpuapp``
+     * ``nrf54l15dk/nrf54l10/cpuapp``
 
 .. _SB_CONFIG_APP_CPUNET_RUN:
 

samples/benchmarks/coremark/boards/app_nrf54l_cpuapp_common.overlay

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/* The following configuration is required to run the CPUFLPR core. */
+&cpuflpr_vpr {
+	status = "okay";
+	execution-memory = <&cpuflpr_sram_code_data>;
+	source-memory = <&cpuflpr_code_partition>;
+};
+
+&cpuapp_vevif_tx {
+	status = "okay";
+};
+
+&uart30 {
+	status = "reserved";
+};

samples/benchmarks/coremark/boards/nrf54l15dk_nrf54l15_cpuapp.overlay

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+ #include "app_aliases_common.overlay"
+ #include "app_nrf54l_cpuapp_common.overlay"
+
+/* The following memory reconfiguration is required to prepare space for CPUFLPR image. */
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			cpuflpr_code_partition: image@165000 {
+				/* FLPR core code partition */
+				reg = <0x165000 DT_SIZE_K(96)>;
+			};
+		};
+
+		cpuflpr_sram_code_data: memory@20028000 {
+			compatible = "mmio-sram";
+			reg = <0x20028000 DT_SIZE_K(96)>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x20028000 0x18000>;
+		};
+	};
+};
+
+&cpuapp_sram {
+	reg = <0x20000000 DT_SIZE_K(160)>;
+	ranges = <0x0 0x20000000 0x28000>;
+};
+
+/* Reserve button and LED related resources for the FLPR core. */
+&gpio0 {
+	status = "reserved";
+};
+
+&gpiote30 {
+	status = "reserved";
+};

samples/benchmarks/coremark/boards/nrf54l15dk_nrf54l15_cpuflpr.conf

@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2025 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+
+CONFIG_COREMARK_ITERATIONS=4000
+
+CONFIG_LOG_MODE_IMMEDIATE=y

samples/benchmarks/coremark/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/ {
+	aliases {
+		button = &button3;
+		led = &led3;
+	};
+ };

samples/benchmarks/coremark/sysbuild.cmake

@@ -5,6 +5,17 @@
 
 include_guard(GLOBAL)
 
+if(SB_CONFIG_APP_CPUFLPR_RUN)
+
+  ExternalZephyrProject_Add(
+    APPLICATION coremark_${SB_CONFIG_FLPRCORE_REMOTE_BOARD_TARGET_CPUCLUSTER}
+    SOURCE_DIR ${APP_DIR}
+    BOARD ${SB_CONFIG_BOARD}/${SB_CONFIG_SOC}/${SB_CONFIG_FLPRCORE_REMOTE_BOARD_TARGET_CPUCLUSTER}
+    BOARD_REVISION ${BOARD_REVISION}
+  )
+
+endif()
+
 if(SB_CONFIG_APP_CPUNET_RUN)
 
   ExternalZephyrProject_Add(