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Processor_design.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 21:48:50 September 13, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Processor_design_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE22F17C6
set_global_assignment -name TOP_LEVEL_ENTITY TOP_MIPS_SS
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:48:50 SEPTEMBER 13, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name SYSTEMVERILOG_FILE RegisterFile.sv
set_global_assignment -name SYSTEMVERILOG_FILE DataMemory.sv
set_global_assignment -name SYSTEMVERILOG_FILE SignExtender.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALU.sv
set_global_assignment -name SYSTEMVERILOG_FILE Mux2to1_32bit.sv
set_global_assignment -name SYSTEMVERILOG_FILE LeftShiftBy2.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALUDecoder.sv
set_global_assignment -name SYSTEMVERILOG_FILE Adder.sv
set_global_assignment -name SYSTEMVERILOG_FILE ResetableFF.sv
set_global_assignment -name SYSTEMVERILOG_FILE mux2.sv
set_global_assignment -name SYSTEMVERILOG_FILE MIPS.sv
set_global_assignment -name SYSTEMVERILOG_FILE Controller.sv
set_global_assignment -name SYSTEMVERILOG_FILE MainDecoder.sv
set_global_assignment -name SYSTEMVERILOG_FILE Datapath.sv
set_global_assignment -name SYSTEMVERILOG_FILE InsructionMemory2.sv
set_global_assignment -name SYSTEMVERILOG_FILE TopMIPS.sv
set_global_assignment -name SYSTEMVERILOG_FILE MIPStestbench.sv
set_global_assignment -name SOURCE_FILE memfile.dat
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name SYSTEMVERILOG_FILE ExtNext.sv
set_global_assignment -name SYSTEMVERILOG_FILE ExtNext_Temp.sv
set_global_assignment -name SYSTEMVERILOG_FILE mux4.sv
set_global_assignment -name SYSTEMVERILOG_FILE Andiestbench.sv
set_global_assignment -name LICENSE_FILE memfile_andi.dat
set_global_assignment -name LICENSE_FILE memfile_jal.dat
set_global_assignment -name LICENSE_FILE memfile_slr.dat
set_global_assignment -name LICENSE_FILE memfile_lbu.dat
set_global_assignment -name LICENSE_FILE memfile_lh_lb.dat
set_global_assignment -name LICENSE_FILE memfile_lhlu.dat
set_global_assignment -name SYSTEMVERILOG_FILE TestbenchLhlb.sv
set_global_assignment -name SYSTEMVERILOG_FILE TestbenchJal.sv
set_global_assignment -name SYSTEMVERILOG_FILE sevenseg.sv
set_global_assignment -name SYSTEMVERILOG_FILE TOP_MIPS_SS.sv
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to memwrite
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top