OpenCAPI-to-PCIe.kicad_sch

(kicad_sch (version 20230121) (generator eeschema)

  (uuid 81468c52-672d-42a3-92d2-29a7c075d013)

  (paper "USLetter")

  (title_block
    (title "OpenCAPI to PCIe x8")
    (rev "A")
    (company "mwrnd")
    (comment 1 "github.com/mwrnd/OpenCAPI-to-PCIe")
  )

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  (text "Same pinout\norder as a\nTC74A0-3.3VAT\nTemperature\nSensor"
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  (text "Vivado defaults to reverse\nChannel-to-Lane ordering;\nX0Y23=TRx0, X0Y22=TRx1, ...\n..., X0Y17=TRx6, X0Y16=TRx7"
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  (text "REFCLK\nis HCSL" (at 75.565 97.155 0)
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  (text "PCIe Signal to OpenCAPI Connector Pin:\nRx7p=B36, Rx7n=B35, Tx7p=A2, Tx7n=A3\nRx6p=B32, Rx6n=B33, Tx6p=B2, Tx6n=B3\nRx5p=A35, Rx5n=A36, Tx5p=A5, Tx5n=A6\nRx4p=B30, Rx4n=B29, Tx4p=B5, Tx4n=B6\nRx3p=B24, Rx3n=B23, Tx3p=B11, Tx3n=B12\nRx2p=A26, Rx2n=A27, Tx2p=A14, Tx2n=A15\nRx1p=B20, Rx1n=B21, Tx1p=B14, Tx1n=B15\nRx0p=A23, Rx0n=A24, Tx0p=A17, Tx0n=A18\n\nRx0p=A23, Rx0n=A24, Tx0p=A17, Tx0n=A18\nRx1p=B20, Rx1n=B21, Tx1p=B14, Tx1n=B15\nRx2p=A26, Rx2n=A27, Tx2p=A14, Tx2n=A15\nRx3p=B24, Rx3n=B23, Tx3p=B11, Tx3n=B12\nRx4p=B30, Rx4n=B29, Tx4p=B5, Tx4n=B6\nRx5p=A35, Rx5n=A36, Tx5p=A5, Tx5n=A6\nRx6p=B32, Rx6n=B33, Tx6p=B2, Tx6n=B3\nRx7p=B36, Rx7n=B35, Tx7p=A2, Tx7n=A3"
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  (text "SlimSAS 8x Cable flips rows of pins.\nRow A connects to Row B and vice versa.\nOpenCAPI AAC FPGA-based Add-In Cards use\nthe Carrier pinout so this adapter uses\nthe Host pinout.\nFPGA_Card_RX = Host_TX = PCIe_TX\nFPGA_Card_TX = Host_RX = PCIe_RX"
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  (text "PRE_DETECT = Presence Detect\n50ohm to GND resistor on\nAdapter Card\n"
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  (text "Through testing I found the\nInnova2 MNV303212A Rev.A2\nhas Rx0, Rx3, and Rx4\ndifferential pairs swapped"
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