The RV32I instruction set architecture defines the base integer instructions for a 32-bit RISC-V computer.
It includes a set of fundamental instructions for integer operations. In this architecture, registers are 32 bits
wide, and all instructions are 32 bits wide. The ISA covers arithmetic and logical operations, load/store instructions
for memory access, control transfer instructions, and memory ordering instructions. Additionally, it provides HINT instructions
for synchronization and memory ordering. The RV32I ISA serves as a foundation for more specialized RISC-V extensions, allowing flexibility
and scalability in system design.