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arm64-gen.c
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/*
* A64 code generator for TCC
*
* Copyright (c) 2014-2015 Edmund Grimley Evans
*
* Copying and distribution of this file, with or without modification,
* are permitted in any medium without royalty provided the copyright
* notice and this notice are preserved. This file is offered as-is,
* without any warranty.
*/
#ifdef TARGET_DEFS_ONLY
// Number of registers available to allocator:
#define NB_REGS 28 // x0-x18, x30, v0-v7
#define TREG_R(x) (x) // x = 0..18
#define TREG_R30 19
#define TREG_F(x) (x + 20) // x = 0..7
// Register classes sorted from more general to more precise:
#define RC_INT (1 << 0)
#define RC_FLOAT (1 << 1)
#define RC_R(x) (1 << (2 + (x))) // x = 0..18
#define RC_R30 (1 << 21)
#define RC_F(x) (1 << (22 + (x))) // x = 0..7
#define RC_IRET (RC_R(0)) // int return register class
#define RC_FRET (RC_F(0)) // float return register class
#define REG_IRET (TREG_R(0)) // int return register number
#define REG_FRET (TREG_F(0)) // float return register number
#define PTR_SIZE 8
#define LDOUBLE_SIZE 16
#define LDOUBLE_ALIGN 16
#define MAX_ALIGN 16
#define CHAR_IS_UNSIGNED
/* define if return values need to be extended explicitely
at caller side (for interfacing with non-TCC compilers) */
#define PROMOTE_RET
/******************************************************/
#else /* ! TARGET_DEFS_ONLY */
/******************************************************/
#define USING_GLOBALS
#include "tcc.h"
#include <assert.h>
ST_DATA const char * const target_machine_defs =
#if defined(__APPLE__)
"__aarch64__\0"
"__arm64__\0"
#else
"__aarch64__\0"
#endif
;
ST_DATA const int reg_classes[NB_REGS] = {
RC_INT | RC_R(0),
RC_INT | RC_R(1),
RC_INT | RC_R(2),
RC_INT | RC_R(3),
RC_INT | RC_R(4),
RC_INT | RC_R(5),
RC_INT | RC_R(6),
RC_INT | RC_R(7),
RC_INT | RC_R(8),
RC_INT | RC_R(9),
RC_INT | RC_R(10),
RC_INT | RC_R(11),
RC_INT | RC_R(12),
RC_INT | RC_R(13),
RC_INT | RC_R(14),
RC_INT | RC_R(15),
RC_INT | RC_R(16),
RC_INT | RC_R(17),
RC_INT | RC_R(18),
RC_R30, // not in RC_INT as we make special use of x30
RC_FLOAT | RC_F(0),
RC_FLOAT | RC_F(1),
RC_FLOAT | RC_F(2),
RC_FLOAT | RC_F(3),
RC_FLOAT | RC_F(4),
RC_FLOAT | RC_F(5),
RC_FLOAT | RC_F(6),
RC_FLOAT | RC_F(7)
};
#define IS_FREG(x) ((x) >= TREG_F(0))
static uint32_t intr(TCCState *S, int r)
{
assert(TREG_R(0) <= r && r <= TREG_R30);
return r < TREG_R30 ? r : 30;
}
static uint32_t fltr(int r)
{
assert(TREG_F(0) <= r && r <= TREG_F(7));
return r - TREG_F(0);
}
// Add an instruction to text section:
ST_FUNC void o(TCCState *S, unsigned int c)
{
int ind1 = S->ind + 4;
if (S->nocode_wanted)
return;
if (ind1 > cur_text_section->data_allocated)
section_realloc(S, cur_text_section, ind1);
write32le(cur_text_section->data + S->ind, c);
S->ind = ind1;
}
static int arm64_encode_bimm64(uint64_t x)
{
int neg = x & 1;
int rep, pos, len;
if (neg)
x = ~x;
if (!x)
return -1;
if (x >> 2 == (x & (((uint64_t)1 << (64 - 2)) - 1)))
rep = 2, x &= ((uint64_t)1 << 2) - 1;
else if (x >> 4 == (x & (((uint64_t)1 << (64 - 4)) - 1)))
rep = 4, x &= ((uint64_t)1 << 4) - 1;
else if (x >> 8 == (x & (((uint64_t)1 << (64 - 8)) - 1)))
rep = 8, x &= ((uint64_t)1 << 8) - 1;
else if (x >> 16 == (x & (((uint64_t)1 << (64 - 16)) - 1)))
rep = 16, x &= ((uint64_t)1 << 16) - 1;
else if (x >> 32 == (x & (((uint64_t)1 << (64 - 32)) - 1)))
rep = 32, x &= ((uint64_t)1 << 32) - 1;
else
rep = 64;
pos = 0;
if (!(x & (((uint64_t)1 << 32) - 1))) x >>= 32, pos += 32;
if (!(x & (((uint64_t)1 << 16) - 1))) x >>= 16, pos += 16;
if (!(x & (((uint64_t)1 << 8) - 1))) x >>= 8, pos += 8;
if (!(x & (((uint64_t)1 << 4) - 1))) x >>= 4, pos += 4;
if (!(x & (((uint64_t)1 << 2) - 1))) x >>= 2, pos += 2;
if (!(x & (((uint64_t)1 << 1) - 1))) x >>= 1, pos += 1;
len = 0;
if (!(~x & (((uint64_t)1 << 32) - 1))) x >>= 32, len += 32;
if (!(~x & (((uint64_t)1 << 16) - 1))) x >>= 16, len += 16;
if (!(~x & (((uint64_t)1 << 8) - 1))) x >>= 8, len += 8;
if (!(~x & (((uint64_t)1 << 4) - 1))) x >>= 4, len += 4;
if (!(~x & (((uint64_t)1 << 2) - 1))) x >>= 2, len += 2;
if (!(~x & (((uint64_t)1 << 1) - 1))) x >>= 1, len += 1;
if (x)
return -1;
if (neg) {
pos = (pos + len) & (rep - 1);
len = rep - len;
}
return ((0x1000 & rep << 6) | (((rep - 1) ^ 31) << 1 & 63) |
((rep - pos) & (rep - 1)) << 6 | (len - 1));
}
static uint32_t arm64_movi(int r, uint64_t x)
{
uint64_t m = 0xffff;
int e;
if (!(x & ~m))
return 0x52800000 | r | x << 5; // movz w(r),#(x)
if (!(x & ~(m << 16)))
return 0x52a00000 | r | x >> 11; // movz w(r),#(x >> 16),lsl #16
if (!(x & ~(m << 32)))
return 0xd2c00000 | r | x >> 27; // movz x(r),#(x >> 32),lsl #32
if (!(x & ~(m << 48)))
return 0xd2e00000 | r | x >> 43; // movz x(r),#(x >> 48),lsl #48
if ((x & ~m) == m << 16)
return (0x12800000 | r |
(~x << 5 & 0x1fffe0)); // movn w(r),#(~x)
if ((x & ~(m << 16)) == m)
return (0x12a00000 | r |
(~x >> 11 & 0x1fffe0)); // movn w(r),#(~x >> 16),lsl #16
if (!~(x | m))
return (0x92800000 | r |
(~x << 5 & 0x1fffe0)); // movn x(r),#(~x)
if (!~(x | m << 16))
return (0x92a00000 | r |
(~x >> 11 & 0x1fffe0)); // movn x(r),#(~x >> 16),lsl #16
if (!~(x | m << 32))
return (0x92c00000 | r |
(~x >> 27 & 0x1fffe0)); // movn x(r),#(~x >> 32),lsl #32
if (!~(x | m << 48))
return (0x92e00000 | r |
(~x >> 43 & 0x1fffe0)); // movn x(r),#(~x >> 32),lsl #32
if (!(x >> 32) && (e = arm64_encode_bimm64(x | x << 32)) >= 0)
return 0x320003e0 | r | (uint32_t)e << 10; // movi w(r),#(x)
if ((e = arm64_encode_bimm64(x)) >= 0)
return 0xb20003e0 | r | (uint32_t)e << 10; // movi x(r),#(x)
return 0;
}
static void arm64_movimm(TCCState *S, int r, uint64_t x)
{
uint32_t i;
if ((i = arm64_movi(r, x)))
o(S, i); // a single MOV
else {
// MOVZ/MOVN and 1-3 MOVKs
int z = 0, m = 0;
uint32_t mov1 = 0xd2800000; // movz
uint64_t x1 = x;
for (i = 0; i < 64; i += 16) {
z += !(x >> i & 0xffff);
m += !(~x >> i & 0xffff);
}
if (m > z) {
x1 = ~x;
mov1 = 0x92800000; // movn
}
for (i = 0; i < 64; i += 16)
if (x1 >> i & 0xffff) {
o(S, mov1 | r | (x1 >> i & 0xffff) << 5 | i << 17);
// movz/movn x(r),#(*),lsl #(i)
break;
}
for (i += 16; i < 64; i += 16)
if (x1 >> i & 0xffff)
o(S, 0xf2800000 | r | (x >> i & 0xffff) << 5 | i << 17);
// movk x(r),#(*),lsl #(i)
}
}
// Patch all branches in list pointed to by t to branch to a:
ST_FUNC void gsym_addr(TCCState *S, int t_, int a_)
{
uint32_t t = t_;
uint32_t a = a_;
while (t) {
unsigned char *ptr = cur_text_section->data + t;
uint32_t next = read32le(ptr);
if (a - t + 0x8000000 >= 0x10000000)
tcc_error(S, "branch out of range");
write32le(ptr, (a - t == 4 ? 0xd503201f : // nop
0x14000000 | ((a - t) >> 2 & 0x3ffffff))); // b
t = next;
}
}
static int arm64_type_size(int t)
{
/*
* case values are in increasing order (from 1 to 11).
* which 'may' help compiler optimizers. See tcc.h
*/
switch (t & VT_BTYPE) {
case VT_BYTE: return 0;
case VT_SHORT: return 1;
case VT_INT: return 2;
case VT_LLONG: return 3;
case VT_PTR: return 3;
case VT_FUNC: return 3;
case VT_STRUCT: return 3;
case VT_FLOAT: return 2;
case VT_DOUBLE: return 3;
case VT_LDOUBLE: return 4;
case VT_BOOL: return 0;
}
assert(0);
return 0;
}
static void arm64_spoff(TCCState *S, int reg, uint64_t off)
{
uint32_t sub = off >> 63;
if (sub)
off = -off;
if (off < 4096)
o(S, 0x910003e0 | sub << 30 | reg | off << 10);
// (add|sub) x(reg),sp,#(off)
else {
arm64_movimm(S, 30, off); // use x30 for offset
o(S, 0x8b3e63e0 | sub << 30 | reg); // (add|sub) x(reg),sp,x30
}
}
/* invert 0: return value to use for store/load */
/* invert 1: return value to use for arm64_sym */
static uint64_t arm64_check_offset(int invert, int sz_, uint64_t off)
{
uint32_t sz = sz_;
if (!(off & ~((uint32_t)0xfff << sz)) ||
(off < 256 || -off <= 256))
return invert ? off : 0ul;
else if ((off & ((uint32_t)0xfff << sz)))
return invert ? off & ((uint32_t)0xfff << sz)
: off & ~((uint32_t)0xfff << sz);
else if (off & 0x1ff)
return invert ? off & 0x1ff : off & ~0x1ff;
else
return invert ? 0ul : off;
}
static void arm64_ldrx(TCCState *S, int sg, int sz_, int dst, int bas, uint64_t off)
{
uint32_t sz = sz_;
if (sz >= 2)
sg = 0;
if (!(off & ~((uint32_t)0xfff << sz)))
o(S, 0x39400000 | dst | bas << 5 | off << (10 - sz) |
(uint32_t)!!sg << 23 | sz << 30); // ldr(*) x(dst),[x(bas),#(off)]
else if (off < 256 || -off <= 256)
o(S, 0x38400000 | dst | bas << 5 | (off & 511) << 12 |
(uint32_t)!!sg << 23 | sz << 30); // ldur(*) x(dst),[x(bas),#(off)]
else {
arm64_movimm(S, 30, off); // use x30 for offset
o(S, 0x38206800 | dst | bas << 5 | (uint32_t)30 << 16 |
(uint32_t)(!!sg + 1) << 22 | sz << 30); // ldr(*) x(dst),[x(bas),x30]
}
}
static void arm64_ldrv(TCCState *S, int sz_, int dst, int bas, uint64_t off)
{
uint32_t sz = sz_;
if (!(off & ~((uint32_t)0xfff << sz)))
o(S, 0x3d400000 | dst | bas << 5 | off << (10 - sz) |
(sz & 4) << 21 | (sz & 3) << 30); // ldr (s|d|q)(dst),[x(bas),#(off)]
else if (off < 256 || -off <= 256)
o(S, 0x3c400000 | dst | bas << 5 | (off & 511) << 12 |
(sz & 4) << 21 | (sz & 3) << 30); // ldur (s|d|q)(dst),[x(bas),#(off)]
else {
arm64_movimm(S, 30, off); // use x30 for offset
o(S, 0x3c606800 | dst | bas << 5 | (uint32_t)30 << 16 |
sz << 30 | (sz & 4) << 21); // ldr (s|d|q)(dst),[x(bas),x30]
}
}
static void arm64_ldrs(TCCState *S, int reg_, int size)
{
uint32_t reg = reg_;
// Use x30 for intermediate value in some cases.
switch (size) {
default: assert(0); break;
case 0:
/* Can happen with zero size structs */
break;
case 1:
arm64_ldrx(S, 0, 0, reg, reg, 0);
break;
case 2:
arm64_ldrx(S, 0, 1, reg, reg, 0);
break;
case 3:
arm64_ldrx(S, 0, 1, 30, reg, 0);
arm64_ldrx(S, 0, 0, reg, reg, 2);
o(S, 0x2a0043c0 | reg | reg << 16); // orr x(reg),x30,x(reg),lsl #16
break;
case 4:
arm64_ldrx(S, 0, 2, reg, reg, 0);
break;
case 5:
arm64_ldrx(S, 0, 2, 30, reg, 0);
arm64_ldrx(S, 0, 0, reg, reg, 4);
o(S, 0xaa0083c0 | reg | reg << 16); // orr x(reg),x30,x(reg),lsl #32
break;
case 6:
arm64_ldrx(S, 0, 2, 30, reg, 0);
arm64_ldrx(S, 0, 1, reg, reg, 4);
o(S, 0xaa0083c0 | reg | reg << 16); // orr x(reg),x30,x(reg),lsl #32
break;
case 7:
arm64_ldrx(S, 0, 2, 30, reg, 0);
arm64_ldrx(S, 0, 2, reg, reg, 3);
o(S, 0x53087c00 | reg | reg << 5); // lsr w(reg), w(reg), #8
o(S, 0xaa0083c0 | reg | reg << 16); // orr x(reg),x30,x(reg),lsl #32
break;
case 8:
arm64_ldrx(S, 0, 3, reg, reg, 0);
break;
case 9:
arm64_ldrx(S, 0, 0, reg + 1, reg, 8);
arm64_ldrx(S, 0, 3, reg, reg, 0);
break;
case 10:
arm64_ldrx(S, 0, 1, reg + 1, reg, 8);
arm64_ldrx(S, 0, 3, reg, reg, 0);
break;
case 11:
arm64_ldrx(S, 0, 2, reg + 1, reg, 7);
o(S, 0x53087c00 | (reg+1) | (reg+1) << 5); // lsr w(reg+1), w(reg+1), #8
arm64_ldrx(S, 0, 3, reg, reg, 0);
break;
case 12:
arm64_ldrx(S, 0, 2, reg + 1, reg, 8);
arm64_ldrx(S, 0, 3, reg, reg, 0);
break;
case 13:
arm64_ldrx(S, 0, 3, reg + 1, reg, 5);
o(S, 0xd358fc00 | (reg+1) | (reg+1) << 5); // lsr x(reg+1), x(reg+1), #24
arm64_ldrx(S, 0, 3, reg, reg, 0);
break;
case 14:
arm64_ldrx(S, 0, 3, reg + 1, reg, 6);
o(S, 0xd350fc00 | (reg+1) | (reg+1) << 5); // lsr x(reg+1), x(reg+1), #16
arm64_ldrx(S, 0, 3, reg, reg, 0);
break;
case 15:
arm64_ldrx(S, 0, 3, reg + 1, reg, 7);
o(S, 0xd348fc00 | (reg+1) | (reg+1) << 5); // lsr x(reg+1), x(reg+1), #8
arm64_ldrx(S, 0, 3, reg, reg, 0);
break;
case 16:
o(S, 0xa9400000 | reg | (reg+1) << 10 | reg << 5);
// ldp x(reg),x(reg+1),[x(reg)]
break;
}
}
static void arm64_strx(TCCState *S, int sz_, int dst, int bas, uint64_t off)
{
uint32_t sz = sz_;
if (!(off & ~((uint32_t)0xfff << sz)))
o(S, 0x39000000 | dst | bas << 5 | off << (10 - sz) | sz << 30);
// str(*) x(dst),[x(bas],#(off)]
else if (off < 256 || -off <= 256)
o(S, 0x38000000 | dst | bas << 5 | (off & 511) << 12 | sz << 30);
// stur(*) x(dst),[x(bas],#(off)]
else {
arm64_movimm(S, 30, off); // use x30 for offset
o(S, 0x38206800 | dst | bas << 5 | (uint32_t)30 << 16 | sz << 30);
// str(*) x(dst),[x(bas),x30]
}
}
static void arm64_strv(TCCState *S, int sz_, int dst, int bas, uint64_t off)
{
uint32_t sz = sz_;
if (!(off & ~((uint32_t)0xfff << sz)))
o(S, 0x3d000000 | dst | bas << 5 | off << (10 - sz) |
(sz & 4) << 21 | (sz & 3) << 30); // str (s|d|q)(dst),[x(bas),#(off)]
else if (off < 256 || -off <= 256)
o(S, 0x3c000000 | dst | bas << 5 | (off & 511) << 12 |
(sz & 4) << 21 | (sz & 3) << 30); // stur (s|d|q)(dst),[x(bas),#(off)]
else {
arm64_movimm(S, 30, off); // use x30 for offset
o(S, 0x3c206800 | dst | bas << 5 | (uint32_t)30 << 16 |
sz << 30 | (sz & 4) << 21); // str (s|d|q)(dst),[x(bas),x30]
}
}
static void arm64_sym(TCCState *S, int r, Sym *sym, unsigned long addend)
{
greloca(S, cur_text_section, sym, S->ind, R_AARCH64_ADR_GOT_PAGE, 0);
o(S, 0x90000000 | r); // adrp xr, #sym
greloca(S, cur_text_section, sym, S->ind, R_AARCH64_LD64_GOT_LO12_NC, 0);
o(S, 0xf9400000 | r | (r << 5)); // ld xr,[xr, #sym]
if (addend) {
// add xr, xr, #addend
if (addend & 0xffful)
o(S, 0x91000000 | r | r << 5 | (addend & 0xfff) << 10);
if (addend > 0xffful) {
// add xr, xr, #addend, lsl #12
if (addend & 0xfff000ul)
o(S, 0x91400000 | r | r << 5 | ((addend >> 12) & 0xfff) << 10);
if (addend > 0xfffffful) {
/* very unlikely */
int t = r ? 0 : 1;
o(S, 0xf81f0fe0 | t); /* str xt, [sp, #-16]! */
arm64_movimm(S, t, addend & ~0xfffffful); // use xt for addent
o(S, 0x91000000 | r | (t << 5)); /* add xr, xt, #0 */
o(S, 0xf84107e0 | t); /* ldr xt, [sp], #16 */
}
}
}
}
static void arm64_load_cmp(TCCState *S, int r, SValue *sv);
ST_FUNC void load(TCCState *S, int r, SValue *sv)
{
int svtt = sv->type.t;
int svr = sv->r & ~VT_BOUNDED;
int svrv = svr & VT_VALMASK;
uint64_t svcul = (uint32_t)sv->c.i;
svcul = svcul >> 31 & 1 ? svcul - ((uint64_t)1 << 32) : svcul;
if (svr == (VT_LOCAL | VT_LVAL)) {
if (IS_FREG(r))
arm64_ldrv(S, arm64_type_size(svtt), fltr(r), 29, svcul);
else
arm64_ldrx(S, !(svtt & VT_UNSIGNED), arm64_type_size(svtt),
intr(S, r), 29, svcul);
return;
}
if (svr == (VT_CONST | VT_LVAL)) {
if (sv->sym)
arm64_sym(S, 30, sv->sym, // use x30 for address
arm64_check_offset(0, arm64_type_size(svtt), sv->c.i));
else
arm64_movimm (S, 30, sv->c.i);
if (IS_FREG(r))
arm64_ldrv(S, arm64_type_size(svtt), fltr(r), 30,
arm64_check_offset(1, arm64_type_size(svtt), sv->c.i));
else
arm64_ldrx(S, !(svtt&VT_UNSIGNED), arm64_type_size(svtt), intr(S, r), 30,
arm64_check_offset(1, arm64_type_size(svtt), sv->c.i));
return;
}
if ((svr & ~VT_VALMASK) == VT_LVAL && svrv < VT_CONST) {
if ((svtt & VT_BTYPE) != VT_VOID) {
if (IS_FREG(r))
arm64_ldrv(S, arm64_type_size(svtt), fltr(r), intr(S, svrv), 0);
else
arm64_ldrx(S, !(svtt & VT_UNSIGNED), arm64_type_size(svtt),
intr(S, r), intr(S, svrv), 0);
}
return;
}
if (svr == (VT_CONST | VT_LVAL | VT_SYM)) {
arm64_sym(S, 30, sv->sym, // use x30 for address
arm64_check_offset(0, arm64_type_size(svtt), svcul));
if (IS_FREG(r))
arm64_ldrv(S, arm64_type_size(svtt), fltr(r), 30,
arm64_check_offset(1, arm64_type_size(svtt), svcul));
else
arm64_ldrx(S, !(svtt&VT_UNSIGNED), arm64_type_size(svtt), intr(S, r), 30,
arm64_check_offset(1, arm64_type_size(svtt), svcul));
return;
}
if (svr == (VT_CONST | VT_SYM)) {
arm64_sym(S, intr(S, r), sv->sym, svcul);
return;
}
if (svr == VT_CONST) {
if ((svtt & VT_BTYPE) != VT_VOID)
arm64_movimm(S, intr(S, r), arm64_type_size(svtt) == 3 ?
sv->c.i : (uint32_t)svcul);
return;
}
if (svr < VT_CONST) {
if (IS_FREG(r) && IS_FREG(svr))
if (svtt == VT_LDOUBLE)
o(S, 0x4ea01c00 | fltr(r) | fltr(svr) << 5);
// mov v(r).16b,v(svr).16b
else
o(S, 0x1e604000 | fltr(r) | fltr(svr) << 5); // fmov d(r),d(svr)
else if (!IS_FREG(r) && !IS_FREG(svr))
o(S, 0xaa0003e0 | intr(S, r) | intr(S, svr) << 16); // mov x(r),x(svr)
else
assert(0);
return;
}
if (svr == VT_LOCAL) {
if (-svcul < 0x1000)
o(S, 0xd10003a0 | intr(S, r) | -svcul << 10); // sub x(r),x29,#...
else {
arm64_movimm(S, 30, -svcul); // use x30 for offset
o(S, 0xcb0003a0 | intr(S, r) | (uint32_t)30 << 16); // sub x(r),x29,x30
}
return;
}
if (svr == VT_JMP || svr == VT_JMPI) {
int t = (svr == VT_JMPI);
arm64_movimm(S, intr(S, r), t);
o(S, 0x14000002); // b .+8
gsym(S, svcul);
arm64_movimm(S, intr(S, r), t ^ 1);
return;
}
if (svr == (VT_LLOCAL | VT_LVAL)) {
arm64_ldrx(S, 0, 3, 30, 29, svcul); // use x30 for offset
if (IS_FREG(r))
arm64_ldrv(S, arm64_type_size(svtt), fltr(r), 30, 0);
else
arm64_ldrx(S, !(svtt & VT_UNSIGNED), arm64_type_size(svtt),
intr(S, r), 30, 0);
return;
}
if (svr == VT_CMP) {
arm64_load_cmp(S, r, sv);
return;
}
printf("load(%x, (%x, %x, %lx))\n", r, svtt, sv->r, (long)svcul);
assert(0);
}
ST_FUNC void store(TCCState *S, int r, SValue *sv)
{
int svtt = sv->type.t;
int svr = sv->r & ~VT_BOUNDED;
int svrv = svr & VT_VALMASK;
uint64_t svcul = (uint32_t)sv->c.i;
svcul = svcul >> 31 & 1 ? svcul - ((uint64_t)1 << 32) : svcul;
if (svr == (VT_LOCAL | VT_LVAL)) {
if (IS_FREG(r))
arm64_strv(S, arm64_type_size(svtt), fltr(r), 29, svcul);
else
arm64_strx(S, arm64_type_size(svtt), intr(S, r), 29, svcul);
return;
}
if (svr == (VT_CONST | VT_LVAL)) {
if (sv->sym)
arm64_sym(S, 30, sv->sym, // use x30 for address
arm64_check_offset(0, arm64_type_size(svtt), sv->c.i));
else
arm64_movimm(S, 30, sv->c.i);
if (IS_FREG(r))
arm64_strv(S, arm64_type_size(svtt), fltr(r), 30,
arm64_check_offset(1, arm64_type_size(svtt), sv->c.i));
else
arm64_strx(S, arm64_type_size(svtt), intr(S, r), 30,
arm64_check_offset(1, arm64_type_size(svtt), sv->c.i));
return;
}
if ((svr & ~VT_VALMASK) == VT_LVAL && svrv < VT_CONST) {
if (IS_FREG(r))
arm64_strv(S, arm64_type_size(svtt), fltr(r), intr(S, svrv), 0);
else
arm64_strx(S, arm64_type_size(svtt), intr(S, r), intr(S, svrv), 0);
return;
}
if (svr == (VT_CONST | VT_LVAL | VT_SYM)) {
arm64_sym(S, 30, sv->sym, // use x30 for address
arm64_check_offset(0, arm64_type_size(svtt), svcul));
if (IS_FREG(r))
arm64_strv(S, arm64_type_size(svtt), fltr(r), 30,
arm64_check_offset(1, arm64_type_size(svtt), svcul));
else
arm64_strx(S, arm64_type_size(svtt), intr(S, r), 30,
arm64_check_offset(1, arm64_type_size(svtt), svcul));
return;
}
printf("store(%x, (%x, %x, %lx))\n", r, svtt, sv->r, (long)svcul);
assert(0);
}
static void arm64_gen_bl_or_b(TCCState *S, int b)
{
if ((S->vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST && (S->vtop->r & VT_SYM)) {
greloca(S, cur_text_section, S->vtop->sym, S->ind,
b ? R_AARCH64_JUMP26 : R_AARCH64_CALL26, 0);
o(S, 0x14000000 | (uint32_t)!b << 31); // b/bl .
}
else {
#ifdef CONFIG_TCC_BCHECK
S->vtop->r &= ~VT_MUSTBOUND;
#endif
o(S, 0xd61f0000 | (uint32_t)!b << 21 | intr(S, gv(S, RC_R30)) << 5); // br/blr
}
}
#if defined(CONFIG_TCC_BCHECK)
static void gen_bounds_call(TCCState *S, int v)
{
Sym *sym = external_helper_sym(S, v);
greloca(S, cur_text_section, sym, S->ind, R_AARCH64_CALL26, 0);
o(S, 0x94000000); // bl
}
static void gen_bounds_prolog(TCCState *S)
{
/* leave some room for bound checking code */
S->func_bound_offset = lbounds_section->data_offset;
S->func_bound_ind = S->ind;
S->func_bound_add_epilog = 0;
o(S, 0xd503201f); /* nop -> mov x0, lbound section pointer */
o(S, 0xd503201f);
o(S, 0xd503201f);
o(S, 0xd503201f); /* nop -> call __bound_local_new */
}
static void gen_bounds_epilog(TCCState *S)
{
addr_t saved_ind;
addr_t *bounds_ptr;
Sym *sym_data;
int offset_modified = S->func_bound_offset != lbounds_section->data_offset;
if (!offset_modified && !S->func_bound_add_epilog)
return;
/* add end of table info */
bounds_ptr = section_ptr_add(S, lbounds_section, sizeof(addr_t));
*bounds_ptr = 0;
sym_data = get_sym_ref(S, &S->char_pointer_type, lbounds_section,
S->func_bound_offset, lbounds_section->data_offset);
/* generate bound local allocation */
if (offset_modified) {
saved_ind = S->ind;
S->ind = S->func_bound_ind;
greloca(S, cur_text_section, sym_data, S->ind, R_AARCH64_ADR_GOT_PAGE, 0);
o(S, 0x90000000 | 0); // adrp x0, #sym_data
greloca(S, cur_text_section, sym_data, S->ind, R_AARCH64_LD64_GOT_LO12_NC, 0);
o(S, 0xf9400000 | 0 | (0 << 5)); // ld x0,[x0, #sym_data]
gen_bounds_call(S, TOK___bound_local_new);
S->ind = saved_ind;
}
/* generate bound check local freeing */
o(S, 0xf81f0fe0); /* str x0, [sp, #-16]! */
o(S, 0x3c9f0fe0); /* str q0, [sp, #-16]! */
greloca(S, cur_text_section, sym_data, S->ind, R_AARCH64_ADR_GOT_PAGE, 0);
o(S, 0x90000000 | 0); // adrp x0, #sym_data
greloca(S, cur_text_section, sym_data, S->ind, R_AARCH64_LD64_GOT_LO12_NC, 0);
o(S, 0xf9400000 | 0 | (0 << 5)); // ld x0,[x0, #sym_data]
gen_bounds_call(S, TOK___bound_local_delete);
o(S, 0x3cc107e0); /* ldr q0, [sp], #16 */
o(S, 0xf84107e0); /* ldr x0, [sp], #16 */
}
#endif
static int arm64_hfa_aux(CType *type, int *fsize, int num)
{
if (is_float(type->t)) {
int a, n = type_size(type, &a);
if (num >= 4 || (*fsize && *fsize != n))
return -1;
*fsize = n;
return num + 1;
}
else if ((type->t & VT_BTYPE) == VT_STRUCT) {
int is_struct = 0; // rather than union
Sym *field;
for (field = type->ref->next; field; field = field->next)
if (field->c) {
is_struct = 1;
break;
}
if (is_struct) {
int num0 = num;
for (field = type->ref->next; field; field = field->next) {
if (field->c != (num - num0) * *fsize)
return -1;
num = arm64_hfa_aux(&field->type, fsize, num);
if (num == -1)
return -1;
}
if (type->ref->c != (num - num0) * *fsize)
return -1;
return num;
}
else { // union
int num0 = num;
for (field = type->ref->next; field; field = field->next) {
int num1 = arm64_hfa_aux(&field->type, fsize, num0);
if (num1 == -1)
return -1;
num = num1 < num ? num : num1;
}
if (type->ref->c != (num - num0) * *fsize)
return -1;
return num;
}
}
else if ((type->t & VT_ARRAY) && ((type->t & VT_BTYPE) != VT_PTR)) {
int num1;
if (!type->ref->c)
return num;
num1 = arm64_hfa_aux(&type->ref->type, fsize, num);
if (num1 == -1 || (num1 != num && type->ref->c > 4))
return -1;
num1 = num + type->ref->c * (num1 - num);
if (num1 > 4)
return -1;
return num1;
}
return -1;
}
static int arm64_hfa(CType *type, unsigned *fsize)
{
if ((type->t & VT_BTYPE) == VT_STRUCT ||
((type->t & VT_ARRAY) && ((type->t & VT_BTYPE) != VT_PTR))) {
int sz = 0;
int n = arm64_hfa_aux(type, &sz, 0);
if (0 < n && n <= 4) {
if (fsize)
*fsize = sz;
return n;
}
}
return 0;
}
static unsigned long arm64_pcs_aux(int n, CType **type, unsigned long *a)
{
int nx = 0; // next integer register
int nv = 0; // next vector register
unsigned long ns = 32; // next stack offset
int i;
for (i = 0; i < n; i++) {
int hfa = arm64_hfa(type[i], 0);
int size, align;
if ((type[i]->t & VT_ARRAY) ||
(type[i]->t & VT_BTYPE) == VT_FUNC)
size = align = 8;
else
size = type_size(type[i], &align);
if (hfa)
// B.2
;
else if (size > 16) {
// B.3: replace with pointer
if (nx < 8)
a[i] = nx++ << 1 | 1;
else {
ns = (ns + 7) & ~7;
a[i] = ns | 1;
ns += 8;
}
continue;
}
else if ((type[i]->t & VT_BTYPE) == VT_STRUCT)
// B.4
size = (size + 7) & ~7;
// C.1
if (is_float(type[i]->t) && nv < 8) {
a[i] = 16 + (nv++ << 1);
continue;
}
// C.2
if (hfa && nv + hfa <= 8) {
a[i] = 16 + (nv << 1);
nv += hfa;
continue;
}
// C.3
if (hfa) {
nv = 8;
size = (size + 7) & ~7;
}
// C.4
if (hfa || (type[i]->t & VT_BTYPE) == VT_LDOUBLE) {
ns = (ns + 7) & ~7;
ns = (ns + align - 1) & -align;
}
// C.5
if ((type[i]->t & VT_BTYPE) == VT_FLOAT)
size = 8;
// C.6
if (hfa || is_float(type[i]->t)) {
a[i] = ns;
ns += size;
continue;
}
// C.7
if ((type[i]->t & VT_BTYPE) != VT_STRUCT && size <= 8 && nx < 8) {
a[i] = nx++ << 1;
continue;
}
// C.8
if (align == 16)
nx = (nx + 1) & ~1;
// C.9
if ((type[i]->t & VT_BTYPE) != VT_STRUCT && size == 16 && nx < 7) {
a[i] = nx << 1;
nx += 2;
continue;
}
// C.10
if ((type[i]->t & VT_BTYPE) == VT_STRUCT && size <= (8 - nx) * 8) {
a[i] = nx << 1;
nx += (size + 7) >> 3;
continue;
}
// C.11
nx = 8;
// C.12
ns = (ns + 7) & ~7;
ns = (ns + align - 1) & -align;
// C.13
if ((type[i]->t & VT_BTYPE) == VT_STRUCT) {
a[i] = ns;
ns += size;
continue;
}
// C.14
if (size < 8)
size = 8;
// C.15
a[i] = ns;
ns += size;
}
return ns - 32;
}
static unsigned long arm64_pcs(int n, CType **type, unsigned long *a)
{
unsigned long stack;
// Return type:
if ((type[0]->t & VT_BTYPE) == VT_VOID)
a[0] = -1;
else {
arm64_pcs_aux(1, type, a);
assert(a[0] == 0 || a[0] == 1 || a[0] == 16);
}
// Argument types:
stack = arm64_pcs_aux(n, type + 1, a + 1);
if (0) {
int i;
for (i = 0; i <= n; i++) {
if (!i)
printf("arm64_pcs return: ");
else
printf("arm64_pcs arg %d: ", i);
if (a[i] == (unsigned long)-1)
printf("void\n");
else if (a[i] == 1 && !i)
printf("X8 pointer\n");
else if (a[i] < 16)
printf("X%lu%s\n", a[i] / 2, a[i] & 1 ? " pointer" : "");
else if (a[i] < 32)
printf("V%lu\n", a[i] / 2 - 8);
else
printf("stack %lu%s\n",
(a[i] - 32) & ~1, a[i] & 1 ? " pointer" : "");
}
}
return stack;
}
ST_FUNC void gfunc_call(TCCState *S, int nb_args)
{
CType *return_type;
CType **t;
unsigned long *a, *a1;
unsigned long stack;
int i;
#ifdef CONFIG_TCC_BCHECK
if (S->do_bounds_check)
gbound_args(S, nb_args);
#endif
return_type = &S->vtop[-nb_args].type.ref->type;
if ((return_type->t & VT_BTYPE) == VT_STRUCT)
--nb_args;
t = tcc_malloc(S, (nb_args + 1) * sizeof(*t));
a = tcc_malloc(S, (nb_args + 1) * sizeof(*a));
a1 = tcc_malloc(S, (nb_args + 1) * sizeof(*a1));
t[0] = return_type;
for (i = 0; i < nb_args; i++)
t[nb_args - i] = &S->vtop[-i].type;
stack = arm64_pcs(nb_args, t, a);
// Allocate space for structs replaced by pointer:
for (i = nb_args; i; i--)
if (a[i] & 1) {
SValue *arg = &S->vtop[i - nb_args];
int align, size = type_size(&arg->type, &align);
assert((arg->type.t & VT_BTYPE) == VT_STRUCT);
stack = (stack + align - 1) & -align;