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stdcells.cdl
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stdcells.cdl
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*
* ******************************************************************************
* * *
* * Copyright (C) 2004-2010, Nangate Inc. *
* * All rights reserved. *
* * *
* * Nangate and the Nangate logo are trademarks of Nangate Inc. *
* * *
* * All trademarks, logos, software marks, and trade names (collectively the *
* * "Marks") in this program are proprietary to Nangate or other respective *
* * owners that have granted Nangate the right and license to use such Marks. *
* * You are not permitted to use the Marks without the prior written consent *
* * of Nangate or such third party that may own the Marks. *
* * *
* * This file has been provided pursuant to a License Agreement containing *
* * restrictions on its use. This file contains valuable trade secrets and *
* * proprietary information of Nangate Inc., and is protected by U.S. and *
* * international laws and/or treaties. *
* * *
* * The copyright notice(s) in this file does not indicate actual or intended *
* * publication of this file. *
* * *
* * NGLibraryCreator, v2010.08-HR32-SP3-2010-08-05 - build 1009061800 *
* * *
* ******************************************************************************
*
*
* Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr).
* Local time is now Fri, 3 Dec 2010, 19:32:12.
* Main process id is 27821.
*
********************************************************************************
* *
* Cellname: AND2_X1. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:24:02 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AND2_X1 A1 A2 ZN VDD VSS
*.PININFO A1:I A2:I ZN:O VDD:P VSS:G
*.EQN ZN=(A1 * A2)
M_i_2 net_0 A1 ZN_neg VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_3 VSS A2 net_0 VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_0 ZN ZN_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4 ZN_neg A1 VDD VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_5 VDD A2 ZN_neg VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_1 ZN ZN_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AND2_X2. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:23:31 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AND2_X2 A1 A2 ZN VDD VSS
*.PININFO A1:I A2:I ZN:O VDD:P VSS:G
*.EQN ZN=(A1 * A2)
M_i_2 net_0 A1 ZN_neg VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3 VSS A2 net_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_0 ZN ZN_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_1 VSS ZN_neg ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4 ZN_neg A1 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5 VDD A2 ZN_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_0 ZN ZN_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_1 VDD ZN_neg ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AND2_X4. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:23:29 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AND2_X4 A1 A2 ZN VDD VSS
*.PININFO A1:I A2:I ZN:O VDD:P VSS:G
*.EQN ZN=(A1 * A2)
M_i_3__m0_m2__m0 net_0__m0_0__m0_0 A2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2__m0_m2__m0 ZN_neg A1 net_0__m0_0__m0_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2__m0_m2__m1 net_0__m0_0__m1 A1 ZN_neg VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3__m0_m2__m1 VSS A2 net_0__m0_0__m1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_0_x4_0 ZN ZN_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_0_x4_3 VSS ZN_neg ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_0_x4_2 ZN ZN_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_0_x4_1 VSS ZN_neg ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_5__m0_x2__m1 ZN_neg A2 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_4__m0_x2__m0 VDD A1 ZN_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_4__m0_x2__m1 ZN_neg A1 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5__m0_x2__m0 VDD A2 ZN_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_0_x4_3 ZN ZN_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_0_x4_0 VDD ZN_neg ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_0_x4_2 ZN ZN_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_0_x4_1 VDD ZN_neg ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AND3_X1. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:18:35 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AND3_X1 A1 A2 A3 ZN VDD VSS
*.PININFO A1:I A2:I A3:I ZN:O VDD:P VSS:G
*.EQN ZN=((A1 * A2) * A3)
M_i_2 net_0 A1 ZN_neg VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_3 net_1 A2 net_0 VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_4 VSS A3 net_1 VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_0 ZN ZN_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_5 VDD A1 ZN_neg VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_6 ZN_neg A2 VDD VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_7 VDD A3 ZN_neg VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_1 ZN ZN_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AND3_X2. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:18:26 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AND3_X2 A1 A2 A3 ZN VDD VSS
*.PININFO A1:I A2:I A3:I ZN:O VDD:P VSS:G
*.EQN ZN=((A1 * A2) * A3)
M_i_2 net_0 A1 ZN_neg VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3 net_1 A2 net_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4 VSS A3 net_1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_0 ZN ZN_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_1 VSS ZN_neg ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_5 VDD A1 ZN_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6 ZN_neg A2 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7 VDD A3 ZN_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_0 ZN ZN_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_1 VDD ZN_neg ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AND3_X4. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:18:25 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AND3_X4 A1 A2 A3 ZN VDD VSS
*.PININFO A1:I A2:I A3:I ZN:O VDD:P VSS:G
*.EQN ZN=((A1 * A2) * A3)
M_i_4__m0_m2__m0 net_1__m0_0__m0_0 A3 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3__m0_m2__m0 net_0__m0_0__m0_0 A2 net_1__m0_0__m0_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2__m0_m2__m0 ZN_neg A1 net_0__m0_0__m0_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2__m0_m2__m1 net_0__m0_0__m1 A1 ZN_neg VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3__m0_m2__m1 net_1__m0_0__m1 A2 net_0__m0_0__m1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4__m0_m2__m1 VSS A3 net_1__m0_0__m1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_0_x4_0 ZN ZN_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_0_x4_1 VSS ZN_neg ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_0_x4_2 ZN ZN_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_0_x4_3 VSS ZN_neg ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_7__m0_x2__m0 ZN_neg A3 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6__m0_x2__m0 VDD A2 ZN_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5__m0_x2__m0 ZN_neg A1 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5__m0_x2__m1 VDD A1 ZN_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6__m0_x2__m1 ZN_neg A2 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7__m0_x2__m1 VDD A3 ZN_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_0_x4_0 ZN ZN_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_0_x4_1 VDD ZN_neg ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_0_x4_2 ZN ZN_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_0_x4_3 VDD ZN_neg ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AND4_X1. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:13:41 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AND4_X1 A1 A2 A3 A4 ZN VDD VSS
*.PININFO A1:I A2:I A3:I A4:I ZN:O VDD:P VSS:G
*.EQN ZN=(((A1 * A2) * A3) * A4)
M_i_2 net_0 A1 ZN_neg VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_3 net_1 A2 net_0 VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_4 net_2 A3 net_1 VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_5 VSS A4 net_2 VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_0 ZN ZN_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_6 ZN_neg A1 VDD VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_7 VDD A2 ZN_neg VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_8 ZN_neg A3 VDD VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_9 VDD A4 ZN_neg VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_1 ZN ZN_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AND4_X2. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:13:36 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AND4_X2 A1 A2 A3 A4 ZN VDD VSS
*.PININFO A1:I A2:I A3:I A4:I ZN:O VDD:P VSS:G
*.EQN ZN=(((A1 * A2) * A3) * A4)
M_i_2 net_0 A1 ZN_neg VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3 net_1 A2 net_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4 net_2 A3 net_1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_5 VSS A4 net_2 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_0 ZN ZN_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_1 VSS ZN_neg ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_6 ZN_neg A1 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7 VDD A2 ZN_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_8 ZN_neg A3 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_9 VDD A4 ZN_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_0 ZN ZN_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_1 VDD ZN_neg ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AND4_X4. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:13:34 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AND4_X4 A1 A2 A3 A4 ZN VDD VSS
*.PININFO A1:I A2:I A3:I A4:I ZN:O VDD:P VSS:G
*.EQN ZN=(((A1 * A2) * A3) * A4)
M_i_5__m0 net_2__m0_0 A4 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4__m0 net_1__m0_0 A3 net_2__m0_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3__m0 net_0__m0_0 A2 net_1__m0_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2__m0 x1 A1 net_0__m0_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2__m1 net_0__m1 A1 x1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3__m1 net_1__m1 A2 net_0__m1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4__m1 net_2__m1 A3 net_1__m1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_5__m1 VSS A4 net_2__m1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_0 ZN x1 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_1 VSS x1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_2 ZN x1 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_3 VSS x1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_9__m0 x1 A4 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_8__m0 VDD A3 x1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7__m0 x1 A2 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6__m0 VDD A1 x1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6__m1 x1 A1 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7__m1 VDD A2 x1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_8__m1 x1 A3 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_9__m1 VDD A4 x1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_0 ZN x1 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_1 VDD x1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_2 ZN x1 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_3 VDD x1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: ANTENNA_X1. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:30:15 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT ANTENNA_X1 A VDD VSS
*.PININFO A:I VDD:P VSS:G
.ENDS
********************************************************************************
* *
* Cellname: AOI211_X1. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:12:12 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AOI211_X1 A B C1 C2 ZN VDD VSS
*.PININFO A:I B:I C1:I C2:I ZN:O VDD:P VSS:G
*.EQN ZN=!(((C1 * C2) + B) + A)
M_i_1 net_0 C2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0 ZN C1 net_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2 VSS B ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3 ZN A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_5 ZN C2 net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_4 net_1 C1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6 net_2 B net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7 VDD A net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AOI211_X2. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:12:11 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AOI211_X2 A B C1 C2 ZN VDD VSS
*.PININFO A:I B:I C1:I C2:I ZN:O VDD:P VSS:G
*.EQN ZN=!(((C1 * C2) + B) + A)
M_i_2__m0 ZN B VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3__m0 VSS A ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3__m1 ZN A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2__m1 VSS B ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m0 net_0__m0_0 C2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m0 ZN C1 net_0__m0_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m1 net_0__m1 C1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m1 VSS C2 net_0__m1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_6__m0 net_2__m0_0 B net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7__m0 VDD A net_2__m0_0 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7__m1 net_2__m1 A VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6__m1 net_1 B net_2__m1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5__m0 ZN C2 net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_4__m0 net_1 C1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_4__m1 ZN C1 net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5__m1 net_1 C2 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AOI211_X4. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:12:03 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AOI211_X4 A B C1 C2 ZN VDD VSS
*.PININFO A:I B:I C1:I C2:I ZN:O VDD:P VSS:G
*.EQN ZN=!(!(!(((C1 * C2) + B) + A)))
M_i_0 net_0 C1 ZN_3 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1 VSS C2 net_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2 ZN_3 B VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3 VSS A ZN_3 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_8_0 ZN_4 ZN_3 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_8_1 VSS ZN_3 ZN_4 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_10_0 ZN ZN_4 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_10_1 VSS ZN_4 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_10_2 ZN ZN_4 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_10_3 VSS ZN_4 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4 ZN_3 C1 net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5 net_1 C2 ZN_3 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6 net_2 B net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7 VDD A net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_9_0 ZN_4 ZN_3 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_9_1 VDD ZN_3 ZN_4 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_11_0 ZN ZN_4 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_11_1 VDD ZN_4 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_11_2 ZN ZN_4 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_11_3 VDD ZN_4 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AOI21_X1. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:18:00 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AOI21_X1 A B1 B2 ZN VDD VSS
*.PININFO A:I B1:I B2:I ZN:O VDD:P VSS:G
*.EQN ZN=!(A + (B1 * B2))
M_i_1 net_0 B2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0 ZN B1 net_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2 VSS A ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4 ZN B2 net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3 net_1 B1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5 VDD A net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AOI21_X2. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:17:40 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AOI21_X2 A B1 B2 ZN VDD VSS
*.PININFO A:I B1:I B2:I ZN:O VDD:P VSS:G
*.EQN ZN=!(A + (B1 * B2))
M_i_2_0_x2_1 ZN A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_0_x2_0 VSS A ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m0_m2__m1 net_0__m0_0__m1 B2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m0_m2__m1 ZN B1 net_0__m0_0__m1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m0_m2__m0 net_0__m0_0__m0_0 B1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m0_m2__m0 VSS B2 net_0__m0_0__m0_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_5_0_x2_0 VDD A net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5_0_x2_1 net_1 A VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_4__m0_x2__m0 ZN B2 net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3__m0_x2__m1 net_1 B1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3__m0_x2__m0 ZN B1 net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_4__m0_x2__m1 net_1 B2 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AOI21_X4. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:17:48 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AOI21_X4 A B1 B2 ZN VDD VSS
*.PININFO A:I B1:I B2:I ZN:O VDD:P VSS:G
*.EQN ZN=!(A + (B1 * B2))
M_i_2_0 ZN A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_1 VSS A ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_2 ZN A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_3 VSS A ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m0 net_0__m0_0 B2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m0 ZN B1 net_0__m0_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m1 net_0__m1 B1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m1 VSS B2 net_0__m1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m2 net_0__m2 B2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m2 ZN B1 net_0__m2 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m3 net_0__m3 B1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m3 VSS B2 net_0__m3 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_5_0 VDD A net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5_1 net_1 A VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5_2 VDD A net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5_3 net_1 A VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_4__m0 ZN B2 net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3__m0 net_1 B1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3__m1 ZN B1 net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_4__m1 net_1 B2 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_4__m2 ZN B2 net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3__m2 net_1 B1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3__m3 ZN B1 net_1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_4__m3 net_1 B2 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AOI221_X1. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:07:32 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AOI221_X1 A B1 B2 C1 C2 ZN VDD VSS
*.PININFO A:I B1:I B2:I C1:I C2:I ZN:O VDD:P VSS:G
*.EQN ZN=!(((C1 * C2) + A) + (B1 * B2))
M_i_4 net_1 B2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3 ZN B1 net_1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2 VSS A ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1 net_0 C2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0 ZN C1 net_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_9 VDD B2 net_3 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_8 net_3 B1 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7 net_2 A net_3 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6 ZN C2 net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5 net_2 C1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AOI221_X2. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:07:38 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AOI221_X2 A B1 B2 C1 C2 ZN VDD VSS
*.PININFO A:I B1:I B2:I C1:I C2:I ZN:O VDD:P VSS:G
*.EQN ZN=!(((C1 * C2) + A) + (B1 * B2))
M_i_2_1 ZN A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3__m0 net_1__m0_0 B1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4__m0 VSS B2 net_1__m0_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4__m1 net_1__m1 B2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3__m1 ZN B1 net_1__m1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_0 VSS A ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m0 net_0__m0_0 C2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m0 ZN C1 net_0__m0_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m1 net_0__m1 C1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m1 VSS C2 net_0__m1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_7_1 net_3 A net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_8__m1 VDD B1 net_3 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_9__m0 net_3 B2 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_9__m1 VDD B2 net_3 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_8__m0 net_3 B1 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7_0 net_2 A net_3 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6__m0 ZN C2 net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5__m1 net_2 C1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5__m0 ZN C1 net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6__m1 net_2 C2 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AOI221_X4. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:07:31 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AOI221_X4 A B1 B2 C1 C2 ZN VDD VSS
*.PININFO A:I B1:I B2:I C1:I C2:I ZN:O VDD:P VSS:G
*.EQN ZN=!(!(!(((C1 * C2) + A) + (B1 * B2))))
M_i_0 net_0 C1 ZN_4 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1 VSS C2 net_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2 ZN_4 A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3 net_1 B1 ZN_4 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4 VSS B2 net_1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_10_0_x2_0 ZN_5 ZN_4 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_10_0_x2_1 VSS ZN_4 ZN_5 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_12_0_x4_0 ZN ZN_5 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_12_0_x4_1 VSS ZN_5 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_12_0_x4_2 ZN ZN_5 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_12_0_x4_3 VSS ZN_5 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_5 ZN_4 C1 net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6 net_2 C2 ZN_4 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7 net_3 A net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_8 VDD B1 net_3 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_9 VDD B2 net_3 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_11_1_x2_1 ZN_5 ZN_4 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_11_1_x2_0 VDD ZN_4 ZN_5 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_13_0_x4_0 ZN ZN_5 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_13_0_x4_1 VDD ZN_5 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_13_0_x4_2 ZN ZN_5 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_13_0_x4_3 VDD ZN_5 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AOI222_X1. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:06:07 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AOI222_X1 A1 A2 B1 B2 C1 C2 ZN VDD VSS
*.PININFO A1:I A2:I B1:I B2:I C1:I C2:I ZN:O VDD:P VSS:G
*.EQN ZN=!(((A1 * A2) + (B1 * B2)) + (C1 * C2))
M_i_5 net_2 C2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4 ZN C1 net_2 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2 net_1 B1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3 VSS B2 net_1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1 net_0 A2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0 ZN A1 net_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_11 net_4 C2 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_10 VDD C1 net_4 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_8 net_4 B1 net_3 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_9 net_3 B2 net_4 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7 ZN A2 net_3 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6 net_3 A1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AOI222_X2. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:06:14 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AOI222_X2 A1 A2 B1 B2 C1 C2 ZN VDD VSS
*.PININFO A1:I A2:I B1:I B2:I C1:I C2:I ZN:O VDD:P VSS:G
*.EQN ZN=!(((A1 * A2) + (B1 * B2)) + (C1 * C2))
M_i_5__m1 net_2__m1 C2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4__m1 ZN C1 net_2__m1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4__m0 net_2__m0_0 C1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_5__m0 VSS C2 net_2__m0_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3__m1 net_1__m1 B2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2__m1 ZN B1 net_1__m1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2__m0 net_1__m0_0 B1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3__m0 VSS B2 net_1__m0_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m0 ZN A1 net_0__m0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m1 net_0__m1 A1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m1 VSS A2 net_0__m1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m0 net_0__m0 A2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_11__m0 VDD C2 net_4 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_10__m0 net_4 C1 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_10__m1 VDD C1 net_4 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_11__m1 net_4 C2 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_9__m1 net_3 B2 net_4 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_8__m0 net_4 B1 net_3 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_8__m1 net_3 B1 net_4 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_9__m0 net_4 B2 net_3 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6__m1 ZN A1 net_3 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6__m0 net_3 A1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7__m1 ZN A2 net_3 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7__m0 net_3 A2 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AOI222_X4. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:05:54 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AOI222_X4 A1 A2 B1 B2 C1 C2 ZN VDD VSS
*.PININFO A1:I A2:I B1:I B2:I C1:I C2:I ZN:O VDD:P VSS:G
*.EQN ZN=!(!(!(((A1 * A2) + (B1 * B2)) + (C1 * C2))))
M_i_0 net_0 A1 ZN_5 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1 VSS A2 net_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3 net_1 B2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2 ZN_5 B1 net_1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4 net_2 C1 ZN_5 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_5 VSS C2 net_2 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_12_0_x2_0 ZN_6 ZN_5 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_12_0_x2_1 VSS ZN_5 ZN_6 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_14_0_x4_0 ZN ZN_6 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_14_0_x4_1 VSS ZN_6 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_14_0_x4_2 ZN ZN_6 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_14_0_x4_3 VSS ZN_6 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_6 ZN_5 A1 net_3 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7 net_3 A2 ZN_5 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_9 net_4 B2 net_3 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_8 net_3 B1 net_4 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_10 net_4 C1 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_11 VDD C2 net_4 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_13_0_x2_0 ZN_6 ZN_5 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_13_0_x2_1 VDD ZN_5 ZN_6 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_15_3_x4_3 ZN ZN_6 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_15_3_x4_2 VDD ZN_6 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_15_3_x4_1 ZN ZN_6 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_15_3_x4_0 VDD ZN_6 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AOI22_X1. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:12:48 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AOI22_X1 A1 A2 B1 B2 ZN VDD VSS
*.PININFO A1:I A2:I B1:I B2:I ZN:O VDD:P VSS:G
*.EQN ZN=!((A1 * A2) + (B1 * B2))
M_i_3 net_1 B2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2 ZN B1 net_1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0 net_0 A1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1 VSS A2 net_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_7 VDD B2 net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6 net_2 B1 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_4 ZN A1 net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5 net_2 A2 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AOI22_X2. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:12:55 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AOI22_X2 A1 A2 B1 B2 ZN VDD VSS
*.PININFO A1:I A2:I B1:I B2:I ZN:O VDD:P VSS:G
*.EQN ZN=!((A1 * A2) + (B1 * B2))
M_i_3__m0 net_1__m0_0 B2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2__m0 ZN B1 net_1__m0_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2__m1 net_1__m1 B1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3__m1 VSS B2 net_1__m1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m0 net_0__m0_0 A2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m0 ZN A1 net_0__m0_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m1 net_0__m1 A1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m1 VSS A2 net_0__m1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_7__m0 VDD B2 net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6__m0 net_2 B1 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6__m1 VDD B1 net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7__m1 net_2 B2 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5__m0 ZN A2 net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_4__m0 net_2 A1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_4__m1 ZN A1 net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5__m1 net_2 A2 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: AOI22_X4. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:13:02 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT AOI22_X4 A1 A2 B1 B2 ZN VDD VSS
*.PININFO A1:I A2:I B1:I B2:I ZN:O VDD:P VSS:G
*.EQN ZN=!((A1 * A2) + (B1 * B2))
M_i_3__m0 net_1__m0_0 B2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2__m0 ZN B1 net_1__m0_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2__m1 net_1__m1 B1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3__m1 VSS B2 net_1__m1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3__m2 net_1__m2 B2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2__m2 ZN B1 net_1__m2 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2__m3 net_1__m3 B1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3__m3 VSS B2 net_1__m3 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m0 net_0__m0_0 A2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m0 ZN A1 net_0__m0_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m1 net_0__m1 A1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m1 VSS A2 net_0__m1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m2 net_0__m2 A2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m2 ZN A1 net_0__m2 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m3 net_0__m3 A1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m3 VSS A2 net_0__m3 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_7__m0 VDD B2 net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6__m0 net_2 B1 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6__m1 VDD B1 net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7__m1 net_2 B2 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7__m2 VDD B2 net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6__m2 net_2 B1 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6__m3 VDD B1 net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7__m3 net_2 B2 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5__m0 ZN A2 net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_4__m0 net_2 A1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_4__m1 ZN A1 net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5__m1 net_2 A2 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5__m2 ZN A2 net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_4__m2 net_2 A1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_4__m3 ZN A1 net_2 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5__m3 net_2 A2 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: BUF_X1. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:29:49 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT BUF_X1 A Z VDD VSS
*.PININFO A:I Z:O VDD:P VSS:G
*.EQN Z=A
M_i_2 VSS A Z_neg VSS NMOS_VTL W=0.210000U L=0.050000U
M_i_0 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3 VDD A Z_neg VDD PMOS_VTL W=0.315000U L=0.050000U
M_i_1 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: BUF_X16. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:29:14 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT BUF_X16 A Z VDD VSS
*.PININFO A:I Z:O VDD:P VSS:G
*.EQN Z=A
M_i_2_0 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_1 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_2 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_3 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_4 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_5 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_6 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_7 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_0 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_1 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_2 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_3 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_4 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_5 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_6 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_7 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_8 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_9 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_10 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_11 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_12 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_13 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_14 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_15 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3_0 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_1 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_2 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_3 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_4 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_5 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_6 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_7 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_0 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_1 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_2 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_3 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_4 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_5 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_6 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_7 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_8 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_9 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_10 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_11 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_12 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_13 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_14 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_15 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: BUF_X2. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:29:48 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT BUF_X2 A Z VDD VSS
*.PININFO A:I Z:O VDD:P VSS:G
*.EQN Z=A
M_i_2 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_0_x2_0 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_0_x2_1 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_0_x2_0 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_0_x2_1 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
********************************************************************************
* *
* Cellname: BUF_X32. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:31:57 on Fri, 3 Dec 2010. *
* *
********************************************************************************
.SUBCKT BUF_X32 A Z VDD VSS
*.PININFO A:I Z:O VDD:P VSS:G
*.EQN Z=A
M_i_2_0 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_1 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_2 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_3 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_4 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_5 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_6 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_7 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_8 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_9 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_10 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_11 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_12 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_13 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_14 Z_neg A VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_15 VSS A Z_neg VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_0 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_1 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_2 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_3 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_4 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_5 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_6 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_7 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_8 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_9 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_10 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_11 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_12 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_13 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_14 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_15 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_16 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_17 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_18 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_19 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_20 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_21 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_22 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_23 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_24 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_25 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_26 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_27 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_28 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_29 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_30 Z Z_neg VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0_31 VSS Z_neg Z VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3_0 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_1 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_2 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_3 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_4 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_5 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_6 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_7 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_8 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_9 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_10 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_11 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_12 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_13 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_14 Z_neg A VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_3_15 VDD A Z_neg VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_0 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_1 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_2 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_3 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_4 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_5 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_6 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_7 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_8 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_9 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_10 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_11 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_12 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_13 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_14 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_15 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_16 Z Z_neg VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_1_17 VDD Z_neg Z VDD PMOS_VTL W=0.630000U L=0.050000U