temp commit 3

checklist.md

@@ -13,8 +13,11 @@
 - [ ] 10: `jal` (internal calculation) and unaligned memory access stall selection (boolean vector); `pc + 4`, `jal` and `pc` next pc.
 - [ ] 11: `jalr` (internal calculation) and unaligned memory access stall selection (explicit naming); `pc + 4`, `jalr` and `pc` next pc.
 - [ ] 12: `jalr` (internal calculation) and unaligned memory access stall selection (boolean vector); `pc + 4`, `jalr` and `pc` next pc.
-- [ ] 13: `jal` and `jalr` (internal calculation), and unaligned memory access stall selection (explicit naming); `pc + 4`, `jalr`, `jal` and `pc` next pc
+- [ ] 13: `jal` and `jalr` (internal calculation), and unaligned memory access stall selection (explicit naming); `pc + 4`, `pc`, `jal` and `jalr` next pc
 - [ ] 14: `jal` and `jalr` (internal calculation), and unaligned memory access stall selection (boolean vector); `pc + 4`, `pc`, `jalr` and `jal` next pc
 - [ ] 15: `branch` and unaligned memory access stall selection (explicit naming); `pc` and `branch` next pc
 - [ ] 16: `jal` and `jalr` (internal calculation), and unaligned memory access stall selection (explicit naming); `pc + 4`, `jalr`, `jal` and `pc` next pc
-- [ ] 17: `jal` and `jalr` (internal calculation), and unaligned memory access stall selection (explicit naming); `pc + 4`, `pc`, `jal` and `jalr` next pc
+- [ ] 17: `jal` and `jalr` (internal calculation), and unaligned memory access stall selection (explicit naming); `pc + 4`, `pc`, `jalr` and `jal` next pc
+- [ ] 18: `jal` and `jalr` (internal calculation), and unaligned memory access stall selection (explicit naming); `pc + 4`, `jalr`, `pc` and `jal` next pc
+- [ ] 19: `jal` and `jalr` (internal calculation), and unaligned memory access stall selection (explicit naming); `pc + 4`, `jal`, `pc` and `jalr` next pc
+- [ ] 20: `jal` and `jalr` (internal calculation), and unaligned memory access stall selection (explicit naming); `pc + 4`, `jal`, `jalr` and `pc` next pc

rtl/fetch_unit/fetch_unit17.v

@@ -0,0 +1,25 @@
+module FetchUnit(
+  input         clock,
+                reset,
+  input  [31:0] io_imm,
+                io_rs1,
+  input         io_stall_en,
+                io_jalr_en,
+                io_jal_en,
+  output [31:0] io_pc
+);
+  reg [31:0] pc;
+  always @(posedge clock) begin
+    if (reset)
+      pc <= 32'h0;
+    else if (io_stall_en) begin
+    end
+    else if (io_jalr_en)
+      pc <= io_rs1 + io_imm;
+    else if (io_jal_en)
+      pc <= pc + io_imm;
+    else
+      pc <= pc + 32'h4;
+  end
+  assign io_pc = pc;
+endmodule

rtl/fetch_unit/fetch_unit18.v

@@ -0,0 +1,25 @@
+module FetchUnit(
+  input         clock,
+                reset,
+  input  [31:0] io_imm,
+                io_rs1,
+  input         io_stall_en,
+                io_jalr_en,
+                io_jal_en,
+  output [31:0] io_pc
+);
+  reg [31:0] pc;
+  always @(posedge clock) begin
+    if (reset)
+      pc <= 32'h0;
+    else if (io_jalr_en)
+      pc <= io_rs1 + io_imm;
+    else if (io_stall_en) begin
+    end
+    else if (io_jal_en)
+      pc <= pc + io_imm;
+    else
+      pc <= pc + 32'h4;
+  end
+  assign io_pc = pc;
+endmodule

rtl/fetch_unit/fetch_unit19.v

@@ -0,0 +1,25 @@
+module FetchUnit(
+  input         clock,
+                reset,
+  input  [31:0] io_imm,
+                io_rs1,
+  input         io_stall_en,
+                io_jalr_en,
+                io_jal_en,
+  output [31:0] io_pc
+);
+  reg [31:0] pc;
+  always @(posedge clock) begin
+    if (reset)
+      pc <= 32'h0;
+    else if (io_jal_en)
+      pc <= pc + io_imm;
+    else if (io_stall_en) begin
+    end
+    else if (io_jalr_en)
+      pc <= io_rs1 + io_imm;
+    else
+      pc <= pc + 32'h4;
+  end
+  assign io_pc = pc;
+endmodule

rtl/fetch_unit/fetch_unit20.v

@@ -0,0 +1,25 @@
+module FetchUnit(
+  input         clock,
+                reset,
+  input  [31:0] io_imm,
+                io_rs1,
+  input         io_stall_en,
+                io_jalr_en,
+                io_jal_en,
+  output [31:0] io_pc
+);
+  reg [31:0] pc;
+  always @(posedge clock) begin
+    if (reset)
+      pc <= 32'h0;
+    else if (io_jal_en)
+      pc <= pc + io_imm;
+    else if (io_jalr_en)
+      pc <= io_rs1 + io_imm;
+    else if (io_stall_en) begin
+    end
+    else
+      pc <= pc + 32'h4;
+  end
+  assign io_pc = pc;
+endmodule

src/main/scala/fetch_unit/FetchUnit17.scala

@@ -21,8 +21,8 @@ class FetchUnit17 extends Module {
 
     pc := MuxCase(pc + 4.U, Seq(
         io.stall_en -> pc,
-        io.jal_en   -> (pc + io.imm.asUInt),
-        io.jalr_en  -> (io.rs1 + io.imm).asUInt
+        io.jalr_en  -> (io.rs1 + io.imm).asUInt,
+        io.jal_en   -> (pc + io.imm.asUInt)
     ))
     io.pc := pc
 }

src/main/scala/fetch_unit/FetchUnit18.scala

@@ -0,0 +1,33 @@
+package fetch_unit
+
+import circt.stage.ChiselStage,
+       chisel3._,
+       chisel3.util._
+
+
+class FetchUnit18 extends Module {
+    //noinspection TypeAnnotation
+    val io = IO(new Bundle {
+        val imm     : SInt = Input(SInt(32.W))
+        val rs1     : SInt = Input(SInt(32.W))
+        val stall_en: Bool = Input(Bool())
+        val jalr_en : Bool = Input(Bool())
+        val jal_en  : Bool = Input(Bool())
+
+        val pc: UInt = Output(UInt(32.W))
+    })
+
+    val pc: UInt = RegInit(0.U(32.W))
+
+    pc := MuxCase(pc + 4.U, Seq(
+        io.jalr_en  -> (io.rs1 + io.imm).asUInt,
+        io.stall_en -> pc,
+        io.jal_en   -> (pc + io.imm.asUInt)
+    ))
+    io.pc := pc
+}
+
+
+object VerilogMain18 extends App {
+    ChiselStage.emitSystemVerilogFile(new FetchUnit18)
+}

src/main/scala/fetch_unit/FetchUnit19.scala

@@ -0,0 +1,33 @@
+package fetch_unit
+
+import circt.stage.ChiselStage,
+       chisel3._,
+       chisel3.util._
+
+
+class FetchUnit19 extends Module {
+    //noinspection TypeAnnotation
+    val io = IO(new Bundle {
+        val imm     : SInt = Input(SInt(32.W))
+        val rs1     : SInt = Input(SInt(32.W))
+        val stall_en: Bool = Input(Bool())
+        val jalr_en : Bool = Input(Bool())
+        val jal_en  : Bool = Input(Bool())
+
+        val pc: UInt = Output(UInt(32.W))
+    })
+
+    val pc: UInt = RegInit(0.U(32.W))
+
+    pc := MuxCase(pc + 4.U, Seq(
+        io.jal_en   -> (pc + io.imm.asUInt),
+        io.stall_en -> pc,
+        io.jalr_en  -> (io.rs1 + io.imm).asUInt
+    ))
+    io.pc := pc
+}
+
+
+object VerilogMain19 extends App {
+    ChiselStage.emitSystemVerilogFile(new FetchUnit19)
+}

src/main/scala/fetch_unit/FetchUnit20.scala

@@ -0,0 +1,33 @@
+package fetch_unit
+
+import circt.stage.ChiselStage,
+       chisel3._,
+       chisel3.util._
+
+
+class FetchUnit20 extends Module {
+    //noinspection TypeAnnotation
+    val io = IO(new Bundle {
+        val imm     : SInt = Input(SInt(32.W))
+        val rs1     : SInt = Input(SInt(32.W))
+        val stall_en: Bool = Input(Bool())
+        val jalr_en : Bool = Input(Bool())
+        val jal_en  : Bool = Input(Bool())
+
+        val pc: UInt = Output(UInt(32.W))
+    })
+
+    val pc: UInt = RegInit(0.U(32.W))
+
+    pc := MuxCase(pc + 4.U, Seq(
+        io.jal_en   -> (pc + io.imm.asUInt),
+        io.jalr_en  -> (io.rs1 + io.imm).asUInt,
+        io.stall_en -> pc,
+    ))
+    io.pc := pc
+}
+
+
+object VerilogMain20 extends App {
+    ChiselStage.emitSystemVerilogFile(new FetchUnit20)
+}