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pong.xise
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pong.xise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="pong.sch" xil_pn:type="FILE_SCHEMATIC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="Ball.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="CollisionManager.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="GenIO.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="InputManager.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="Player.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="PlayerTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="PowerUp.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="PS2_Kbd.ngc" xil_pn:type="FILE_NGC">
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<file xil_pn:name="PS2_USB_SDC.ucf" xil_pn:type="FILE_UCF">
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<file xil_pn:name="RandGen.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="RenderManager.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="PlayerTest_shouldResetScore.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="PlayerTest_shouldSpeedUpToMaxSpeed.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="PlayerTest_shouldSizeDown.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="PlayerTest_shouldMoveUpAndDown.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="PowerUpTest_shouldGenerateRandomPowerUp.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="BallTest_shouldChangeSpeedAndSize.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="68"/>
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<file xil_pn:name="BallTest_shouldMoveByVector.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="78"/>
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<file xil_pn:name="CollisionManagerTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="64"/>
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<file xil_pn:name="RandGenTest.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="CollisionaManagerTest_shouldHitRightWall.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="86"/>
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<file xil_pn:name="CollisionManagerTest_shouldHitLeftWall.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="94"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="94"/>
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<file xil_pn:name="GameLogic.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="GameLogic_shouldEndGame.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="GameLogic_shouldResetGame.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="87"/>
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<properties>
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<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/>
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<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
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