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Copy pathbreakoutTop.ucf
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breakoutTop.ucf
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# Clock
NET "clk" LOC="B8";
# Define a new timing constraint indicating a 50 MHz clock period
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50 %;
# Attach sw(0) to the switch 0 (SW0)
#NET "sw<0>" LOC=G18;
# Attach sw(1) to the switch 1 (SW1)
#NET "sw<1>" LOC=H18;
# Attach sw(2) to the switch 2 (SW2)
#NET "sw<2>" LOC=K18;
# Attach sw(3) to the switch 3 (SW3)
#NET "sw<3>" LOC=K17;
# Attach sw(4) to the switch 4 (SW4)
#NET "sw<4>" LOC=L14;
# Attach sw(5) to the switch 5 (SW5)
#NET "sw<5>" LOC=L13;
# Attach sw(6) to the switch 6 (SW6)
#NET "sw<6>" LOC=N17;
# Attach sw(7) to the switch 7 (SW7)
#NET "sw<7>" LOC=R17;
# Attach btn(0) to the button 0 (BTN0)
NET "btn<0>" LOC=B18;
# Attach btn(1) to the button 1 (BTN1)
NET "btn<1>" LOC=D18;
# Attach btn(2) to the button 2 (BTN2)
NET "btn<2>" LOC=E18;
# Attach btn(3) to the button 3 (BTN3)
NET "btn<3>" LOC=H13;
# Attach led(0) to the output LED 0 (LD0)
#NET "led<0>" LOC=J14;
# Attach led(1) to the output LED 1 (LD1)
#NET "led<1>" LOC=J15;
# Attach led(2) to the output LED 2 (LD2)
#NET "led<2>" LOC=K15;
# Attach led(3) to the output LED 3 (LD3)
#NET "led<3>" LOC=K14;
# Attach led(4) to the output LED 4 (LD4)
#NET "led<4>" LOC=E17;
# Attach led(5) to the output LED 5 (LD5)
#NET "led<5>" LOC=P15;
# Attach led(6) to the output LED 6 (LD6)
#NET "led<6>" LOC=F4;
# Attach led(7) to the output LED 7 (LD7)
#NET "led<7>" LOC=R4;
# Attach seg(0) to the output SEG 0
NET "seg<0>" LOC=L18;
# Attach seg(1) to the output SEG 1
NET "seg<1>" LOC=F18;
# Attach seg(2) to the output SEG 2
NET "seg<2>" LOC=D17;
# Attach led(3) to the output SEG 3
NET "seg<3>" LOC=D16;
# Attach led(4) to the output SEG 4
NET "seg<4>" LOC=G14;
# Attach led(5) to the output SEG 5
NET "seg<5>" LOC=J17;
# Attach led(6) to the output SEG 6
NET "seg<6>" LOC=H14;
# Attach DP to the output DP
NET "dp" LOC=C17;
# Attach an(0) to the anode 0 (AN0)
NET "an<0>" LOC=F17;
# Attach an(1) to the anode 1 (AN1)
NET "an<1>" LOC=H17;
# Attach an(2) to the anode 2 (AN2)
NET "an<2>" LOC=C18;
# Attach an(3) to the anode 3 (AN3)
NET "an<3>" LOC=F15;
# Attach Hsync to the output HS
NET "Hsync" LOC=T4;
# Attach Vsync to the output VS
NET "Vsync" LOC=U3;
# Attach vgaRed to the output RED
NET "vgaRed<0>" LOC=R9;
NET "vgaRed<1>" LOC=T8;
NET "vgaRed<2>" LOC=R8;
# Attach vgaGreen to the output GRN
NET "vgaGreen<0>" LOC=N8;
NET "vgaGreen<1>" LOC=P8;
NET "vgaGreen<2>" LOC=P6;
# Attach vgaBlue to the output BLU
NET "vgaBlue<0>" LOC=U5;
NET "vgaBlue<1>" LOC=U4;
## onBoard Cellular RAM and StrataFlash
NET "MemOE" LOC = "T2"; # Bank = 3, Pin name = IO_L24P_3, Type = I/O, Sch name = OE
NET "MemWR" LOC = "N7"; # Bank = 2, Pin name = IO_L07P_2, Type = I/O, Sch name = WE
NET "RamAdv" LOC = "J4"; # Bank = 3, Pin name = IO_L11N_3/LHCLK1, Type = LHCLK, Sch name = MT-ADV
NET "RamCS" LOC = "R6"; # Bank = 2, Pin name = IO_L05P_2, Type = I/O, Sch name = MT-CE
NET "RamClk" LOC = "H5"; # Bank = 3, Pin name = IO_L08N_3, Type = I/O, Sch name = MT-CLK
NET "RamCRE" LOC = "P7"; # Bank = 2, Pin name = IO_L07N_2, Type = I/O, Sch name = MT-CRE
NET "RamLB" LOC = "K5"; # Bank = 3, Pin name = IO_L14N_3/LHCLK7, Type = LHCLK, Sch name = MT-LB
NET "RamUB" LOC = "K4"; # Bank = 3, Pin name = IO_L13N_3/LHCLK5, Type = LHCLK, Sch name = MT-UB
NET "MemAdr<0>" LOC = "J1"; # Bank = 3, Pin name = IO_L12P_3/LHCLK2, Type = LHCLK, Sch name = ADR1
NET "MemAdr<1>" LOC = "J2"; # Bank = 3, Pin name = IO_L12N_3/LHCLK3/IRDY2, Type = LHCLK, Sch name = ADR2
NET "MemAdr<2>" LOC = "H4"; # Bank = 3, Pin name = IO_L09P_3, Type = I/O, Sch name = ADR3
NET "MemAdr<3>" LOC = "H1"; # Bank = 3, Pin name = IO_L10N_3, Type = I/O, Sch name = ADR4
NET "MemAdr<4>" LOC = "H2"; # Bank = 3, Pin name = IO_L10P_3, Type = I/O, Sch name = ADR5
NET "MemAdr<5>" LOC = "J5"; # Bank = 3, Pin name = IO_L11P_3/LHCLK0, Type = LHCLK, Sch name = ADR6
NET "MemAdr<6>" LOC = "H3"; # Bank = 3, Pin name = IO_L09N_3, Type = I/O, Sch name = ADR7
NET "MemAdr<7>" LOC = "H6"; # Bank = 3, Pin name = IO_L08P_3, Type = I/O, Sch name = ADR8
NET "MemAdr<8>" LOC = "F1"; # Bank = 3, Pin name = IO_L05P_3, Type = I/O, Sch name = ADR9
NET "MemAdr<9>" LOC = "G3"; # Bank = 3, Pin name = IO_L06P_3, Type = I/O, Sch name = ADR10
NET "MemAdr<10>" LOC = "G6"; # Bank = 3, Pin name = IO_L07P_3, Type = I/O, Sch name = ADR11
NET "MemAdr<11>" LOC = "G5"; # Bank = 3, Pin name = IO_L07N_3, Type = I/O, Sch name = ADR12
NET "MemAdr<12>" LOC = "G4"; # Bank = 3, Pin name = IO_L06N_3/VREF_3, Type = VREF, Sch name = ADR13
NET "MemAdr<13>" LOC = "F2"; # Bank = 3, Pin name = IO_L05N_3, Type = I/O, Sch name = ADR14
NET "MemAdr<14>" LOC = "E1"; # Bank = 3, Pin name = IO_L03N_3, Type = I/O, Sch name = ADR15
NET "MemAdr<15>" LOC = "M5"; # Bank = 3, Pin name = IO_L19P_3, Type = I/O, Sch name = ADR16
NET "MemAdr<16>" LOC = "E2"; # Bank = 3, Pin name = IO_L03P_3, Type = I/O, Sch name = ADR17
NET "MemAdr<17>" LOC = "C2"; # Bank = 3, Pin name = IO_L01N_3, Type = I/O, Sch name = ADR18
NET "MemAdr<18>" LOC = "C1"; # Bank = 3, Pin name = IO_L01P_3, Type = I/O, Sch name = ADR19
NET "MemAdr<19>" LOC = "D2"; # Bank = 3, Pin name = IO_L02N_3/VREF_3, Type = VREF, Sch name = ADR20
NET "MemAdr<20>" LOC = "K3"; # Bank = 3, Pin name = IO_L13P_3/LHCLK4/TRDY2, Type = LHCLK, Sch name = ADR21
NET "MemAdr<21>" LOC = "D1"; # Bank = 3, Pin name = IO_L02P_3, Type = I/O, Sch name = ADR22
NET "MemAdr<22>" LOC = "K6"; # Bank = 3, Pin name = IO_L14P_3/LHCLK6, Type = LHCLK, Sch name = ADR23
NET "MemDB<0>" LOC = "L1"; # Bank = 3, Pin name = IO_L15P_3, Type = I/O, Sch name = DB0
NET "MemDB<1>" LOC = "L4"; # Bank = 3, Pin name = IO_L16N_3, Type = I/O, Sch name = DB1
NET "MemDB<2>" LOC = "L6"; # Bank = 3, Pin name = IO_L17P_3, Type = I/O, Sch name = DB2
NET "MemDB<3>" LOC = "M4"; # Bank = 3, Pin name = IO_L18P_3, Type = I/O, Sch name = DB3
NET "MemDB<4>" LOC = "N5"; # Bank = 3, Pin name = IO_L20N_3, Type = I/O, Sch name = DB4
NET "MemDB<5>" LOC = "P1"; # Bank = 3, Pin name = IO_L21N_3, Type = I/O, Sch name = DB5
NET "MemDB<6>" LOC = "P2"; # Bank = 3, Pin name = IO_L21P_3, Type = I/O, Sch name = DB6
NET "MemDB<7>" LOC = "R2"; # Bank = 3, Pin name = IO_L23N_3, Type = I/O, Sch name = DB7
NET "MemDB<8>" LOC = "L3"; # Bank = 3, Pin name = IO_L16P_3, Type = I/O, Sch name = DB8
NET "MemDB<9>" LOC = "L5"; # Bank = 3, Pin name = IO_L17N_3/VREF_3, Type = VREF, Sch name = DB9
NET "MemDB<10>" LOC = "M3"; # Bank = 3, Pin name = IO_L18N_3, Type = I/O, Sch name = DB10
NET "MemDB<11>" LOC = "M6"; # Bank = 3, Pin name = IO_L19N_3, Type = I/O, Sch name = DB11
NET "MemDB<12>" LOC = "L2"; # Bank = 3, Pin name = IO_L15N_3, Type = I/O, Sch name = DB12
NET "MemDB<13>" LOC = "N4"; # Bank = 3, Pin name = IO_L20P_3, Type = I/O, Sch name = DB13
NET "MemDB<14>" LOC = "R3"; # Bank = 3, Pin name = IO_L23P_3, Type = I/O, Sch name = DB14
NET "MemDB<15>" LOC = "T1"; # Bank = 3, Pin name = IO_L24N_3, Type = I/O, Sch name = DB15