Import latest changes from Darjeeling

docs/opentitan/darjeeling.md

@@ -104,10 +104,10 @@ any useful feature (only allow guest test code to execute as expected).
 
 ````sh
 qemu-system-riscv32 -M ot-darjeeling,no_epmp_cfg=true -display none -serial mon:stdio \
-  -global ot-ibex_wrapper-dj.lc-ignore=on -kernel hello.elf
+  -global ot-ibex_wrapper.lc-ignore=on -kernel hello.elf
 ````
 See the section "Useful execution options" for documentation about the `no_epmp_cfg` and
-`ot-ibex_wrapper-dj.lc-ignore=on` option.
+`ot-ibex_wrapper.lc-ignore=on` option.
 
 ### Boot sequence ROM, ROM_EXT, BLO
 
@@ -149,14 +149,14 @@ See [`tools.md`](tools.md)
   to update the vCPU reset vector at startup. When this option is used, with `-kernel` option for
   example, the application is loaded in memory but the default machine reset vector is used.
 
-* `-global ot-ibex_wrapper-dj.lc-ignore=on` should be used whenever no OTP image is provided, or if
+* `-global ot-ibex_wrapper.lc-ignore=on` should be used whenever no OTP image is provided, or if
   the current LifeCycle state stored in the OTP image does not allow the Ibex core to fetch data.
   This switch forces the Ibex core to execute whatever the LifeCycle broadcasted signal, which
   departs from the HW behavior but maybe helpful to run the machine without a full OTP set up. The
   alternative to allow the Ibex core to execute guest code is to provide a valid OTP image with one
   of the expected LifeCycle state, such as TestUnlock*, Dev, Prod or RMA.
 
-* `-global ot-ibex_wrapper-dj.lc-ignore-ids=<ids>` acts as `lc-ignore`, enabling the selection of
+* `-global ot-ibex_wrapper.lc-ignore-ids=<ids>` acts as `lc-ignore`, enabling the selection of
   specific ibex wrapper instance based on their unique identifiers. See `ot_id` property in the
   machine definition file for a list of valid identifiers. `<ids>` should be defined as a comma-
   separated list of valid identifiers. It is only possible to ignore LifeCycle states with this
@@ -205,6 +205,20 @@ virtual machine. It contains three ASCII chars `QMU` followed with a configurabl
 the MSB, whose meaning is not defined. It can be any 8-byte value, and defaults to 0x0. To configure
 this version field, use the `qemu_version` property of the Ibex Wrapper device.
 
+There are two modes to handle address remapping, with different limitations:
+
+- default mode: use an MMU-like implementation (via ot_vmapper) to remap addresses. This mode
+  enables to remap instruction accesses and data accesses independently, as the real HW. However,
+  due to QEMU limitations, addresses and mapped region sizes should be aligned and multiple of 4096
+  bytes, i.e. a standard MMU page size. This is the recommended mode.
+
+- legacy mode: This mode has no address nor size limitations, however it cannot distinguish
+  instruction accesses from data accesses, which means that both kind of accesses must be defined
+  for each active remapping slot for the remapping to be enabled. Moreover it relies on MemoryRegion
+  aliasing and may not be as robust as the default mode. It is recommended to use the default mode
+  whenever possible. To enable this legacy mode, set the `alias-mode` property to true:
+  `-global ot-ibex_wrapper.alias-mode=true`
+
 ### OTBN
 
 * `-global ot-otbn.logfile=<filename>` dumps executed instructions on OTBN core into the specified

docs/opentitan/earlgrey.md

@@ -156,6 +156,27 @@ See [`tools.md`](tools.md)
   Note: MTD bus 2 is assigned to the internal controller with the embedded flash storage. See also
   the SPI Host section.
 
+### Ibex Wrapper
+
+The `FPGA_INFO` register of the Ibex Wrapper device is used to report that the HW platform is a QEMU
+virtual machine. It contains three ASCII chars `QMU` followed with a configurable _version_ field in
+the MSB, whose meaning is not defined. It can be any 8-byte value, and defaults to 0x0. To configure
+this version field, use the `qemu_version` property of the Ibex Wrapper device.
+
+There are two modes to handle address remapping, with different limitations:
+
+- default mode: use an MMU-like implementation (via ot_vmapper) to remap addresses. This mode
+  enables to remap instruction accesses and data accesses independently, as the real HW. However,
+  due to QEMU limitations, addresses and mapped region sizes should be aligned and multiple of 4096
+  bytes, i.e. a standard MMU page size. This is the recommended mode.
+
+- legacy mode: This mode has no address nor size limitations, however it cannot distinguish
+  instruction accesses from data accesses, which means that both kind of accesses must be defined
+  for each active remapping slot for the remapping to be enabled. Moreover it relies on MemoryRegion
+  aliasing and may not be as robust as the default mode. It is recommended to use the default mode
+  whenever possible. To enable this legacy mode, set the `alias-mode` property to true:
+  `-global ot-ibex_wrapper.alias-mode=true`
+
 ### OTBN
 
 * `-global ot-otbn.logfile=<filename>` output OTBN execution message to the specified logfile. When

docs/opentitan/spidevflash.md

@@ -6,8 +6,8 @@
 
 ````text
 usage: spidevflash.py [-h] -f FILE [-a ADDRESS] [-S SOCKET] [-R RETRY_COUNT]
-                      [-T SYNC_TIME] [-r HOST] [-p PORT] [--log-udp UDP_PORT]
-                      [-v] [-d]
+                      [-T SYNC_TIME] [--idle DELAY] [-t] [-r HOST] [-p PORT]
+                      [--log-udp UDP_PORT] [-v] [-d]
 
 SPI device flasher tool.
 
@@ -21,6 +21,8 @@ options:
                         connection retry count (default: 1)
   -T, --sync-time SYNC_TIME
                         synchronization max time (default: 5.0s)
+  --idle DELAY          stay idle before establish connection
+  -t, --terminate       terminate QEMU VM on completion
   -r, --host HOST       remote host name (default: localhost)
   -p, --port PORT       remote host TCP port (default: 8004)
   --log-udp UDP_PORT    Log to a local UDP logger
@@ -52,6 +54,9 @@ options:
 
 * `-v` can be repeated to increase verbosity of the script, mostly for debug purpose.
 
+* `--idle` wait for the specified delay in seconds before attempting a connection to the QEMU SPI
+   device socket
+
 * `--log-udp` specify a UDP port on the local host to redirect log messages,
 
 ### Examples

hw/opentitan/Kconfig

@@ -63,14 +63,7 @@ config OT_I2C_DJ
     bool
 
 config OT_IBEX_WRAPPER
-    bool
-
-config OT_IBEX_WRAPPER_DJ
-    select OT_IBEX_WRAPPER
-    bool
-
-config OT_IBEX_WRAPPER_EG
-    select OT_IBEX_WRAPPER
+    select OT_VMAPPER
     bool
 
 config OT_KMAC
@@ -167,4 +160,7 @@ config OT_UART
 config OT_UNIMP
     bool
 
+config OT_VMAPPER
+    bool
+
 source otbn/Kconfig

hw/opentitan/meson.build

@@ -24,8 +24,6 @@ system_ss.add(when: 'CONFIG_OT_GPIO_EG', if_true: files('ot_gpio_eg.c'))
 system_ss.add(when: 'CONFIG_OT_HMAC', if_true: [files('ot_hmac.c'), libtomcrypt_dep])
 system_ss.add(when: 'CONFIG_OT_I2C_DJ', if_true: files('ot_i2c_dj.c'))
 system_ss.add(when: 'CONFIG_OT_IBEX_WRAPPER', if_true: files('ot_ibex_wrapper.c'))
-system_ss.add(when: 'CONFIG_OT_IBEX_WRAPPER_DJ', if_true: files('ot_ibex_wrapper_dj.c'))
-system_ss.add(when: 'CONFIG_OT_IBEX_WRAPPER_EG', if_true: files('ot_ibex_wrapper_eg.c'))
 system_ss.add(when: 'CONFIG_OT_KMAC', if_true: [files('ot_kmac.c'), libtomcrypt_dep])
 system_ss.add(when: 'CONFIG_OT_LC_CTRL', if_true: files('ot_lc_ctrl.c'))
 system_ss.add(when: 'CONFIG_OT_MBX', if_true: files('ot_mbx.c'))
@@ -55,4 +53,6 @@ system_ss.add(when: 'CONFIG_OT_TIMER', if_true: files('ot_timer.c'))
 system_ss.add(when: 'CONFIG_OT_UART', if_true: files('ot_uart.c'))
 system_ss.add(when: 'CONFIG_OT_UNIMP', if_true: files('ot_unimp.c'))
 
+riscv_ss.add(when: 'CONFIG_OT_VMAPPER', if_true: files('ot_vmapper.c'))
+
 subdir('otbn')

hw/opentitan/ot_aes.c

@@ -1,7 +1,7 @@
 /*
  * QEMU OpenTitan AES device
  *
- * Copyright (c) 2022-2024 Rivos, Inc.
+ * Copyright (c) 2022-2025 Rivos, Inc.
  * Copyright (c) 2025 lowRISC contributors.
  *
  * Author(s):
@@ -256,6 +256,11 @@ struct OtAESState {
     bool fast_mode;
 };
 
+struct OtAESClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
 #ifdef DEBUG_AES
 static const char *ot_aes_hexdump(OtAESState *s, const uint8_t *buf,
                                   size_t size)
@@ -1284,18 +1289,18 @@ static const MemoryRegionOps ot_aes_regs_ops = {
     .impl.max_access_size = 4u,
 };
 
-static void ot_aes_reset(DeviceState *dev)
+static void ot_aes_reset_enter(Object *obj, ResetType type)
 {
-    OtAESState *s = OT_AES(dev);
-    OtAESRegisters *r = s->regs;
+    OtAESClass *c = OT_AES_GET_CLASS(obj);
+    OtAESState *s = OT_AES(obj);
     OtAESEDN *e = &s->edn;
+    OtAESRegisters *r = s->regs;
 
-    timer_del(s->retard_timer);
-
-    g_assert(e->device);
-    g_assert(e->ep != UINT8_MAX);
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
 
-    s->prng = ot_prng_allocate();
+    timer_del(s->retard_timer);
 
     memset(s->ctx, 0, sizeof(*s->ctx));
     memset(r, 0, sizeof(*r));
@@ -1312,11 +1317,36 @@ static void ot_aes_reset(DeviceState *dev)
     for (unsigned ix = 0; ix < PARAM_NUM_ALERTS; ix++) {
         ibex_irq_set(&s->alerts[ix], 0);
     }
+}
+
+static void ot_aes_reset_exit(Object *obj, ResetType type)
+{
+    OtAESClass *c = OT_AES_GET_CLASS(obj);
+    OtAESState *s = OT_AES(obj);
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    qemu_bh_cancel(s->process_bh);
 
     trace_ot_aes_reseed("reset");
     ot_aes_handle_trigger(s);
 }
 
+static void ot_aes_realize(DeviceState *dev, Error **errp)
+{
+    OtAESState *s = OT_AES(dev);
+    OtAESEDN *e = &s->edn;
+
+    (void)errp;
+
+    g_assert(e->device);
+    g_assert(e->ep != UINT8_MAX);
+
+    s->prng = ot_prng_allocate();
+}
+
 static void ot_aes_init(Object *obj)
 {
     OtAESState *s = OT_AES(obj);
@@ -1349,16 +1379,22 @@ static void ot_aes_class_init(ObjectClass *klass, void *data)
     DeviceClass *dc = DEVICE_CLASS(klass);
     (void)data;
 
-    device_class_set_legacy_reset(dc, &ot_aes_reset);
+    dc->realize = &ot_aes_realize;
     device_class_set_props(dc, ot_aes_properties);
     set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtAESClass *ac = OT_AES_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_aes_reset_enter, NULL,
+                                       &ot_aes_reset_exit, &ac->parent_phases);
 }
 
 static const TypeInfo ot_aes_info = {
     .name = TYPE_OT_AES,
     .parent = TYPE_SYS_BUS_DEVICE,
     .instance_size = sizeof(OtAESState),
     .instance_init = &ot_aes_init,
+    .class_size = sizeof(OtAESClass),
     .class_init = &ot_aes_class_init,
 };
 

hw/opentitan/ot_alert.c

@@ -1,7 +1,7 @@
 /*
  * QEMU OpenTitan Alert handler device
  *
- * Copyright (c) 2023-2024 Rivos, Inc.
+ * Copyright (c) 2023-2025 Rivos, Inc.
  *
  * Author(s):
  *  Emmanuel Blot <eblot@rivosinc.com>
@@ -237,6 +237,11 @@ struct OtAlertState {
     uint8_t n_classes;
 };
 
+struct OtAlertClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
 /* clang-format off */
 #define ST_NAME_ENTRY(_name_) [STATE_##_name_] = stringify(_name_)
 #define ST_NAME(_st_) ((_st_) < ARRAY_SIZE(ST_NAMES) ? ST_NAMES[(_st_)] : "?")
@@ -955,7 +960,7 @@ static void ot_alert_fill_access_table(OtAlertState *s)
 }
 
 static Property ot_alert_properties[] = {
-    DEFINE_PROP_STRING("ot_id", OtAlertState, ot_id),
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtAlertState, ot_id),
     DEFINE_PROP_UINT16("n_alerts", OtAlertState, n_alerts, 0),
     DEFINE_PROP_UINT8("n_lpg", OtAlertState, n_low_power_groups, 1u),
     DEFINE_PROP_UINT8("n_classes", OtAlertState, n_classes, 4u),
@@ -973,11 +978,17 @@ static const MemoryRegionOps ot_alert_regs_ops = {
     .impl.max_access_size = 4u,
 };
 
-static void ot_alert_reset(DeviceState *dev)
+static void ot_alert_reset_enter(Object *obj, ResetType type)
 {
-    OtAlertState *s = OT_ALERT(dev);
+    OtAlertClass *c = OT_ALERT_GET_CLASS(obj);
+    OtAlertState *s = OT_ALERT(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
 
     for (unsigned ix = 0; ix < s->n_classes; ix++) {
+        qemu_bh_cancel(s->schedulers[ix].esc_releaser);
         timer_del(&s->schedulers[ix].timer);
     }
 
@@ -1150,16 +1161,21 @@ static void ot_alert_class_init(ObjectClass *klass, void *data)
     DeviceClass *dc = DEVICE_CLASS(klass);
     (void)data;
 
-    device_class_set_legacy_reset(dc, &ot_alert_reset);
     dc->realize = &ot_alert_realize;
     device_class_set_props(dc, ot_alert_properties);
     set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtAlertClass *ac = OT_ALERT_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_alert_reset_enter, NULL, NULL,
+                                       &ac->parent_phases);
 }
 
 static const TypeInfo ot_alert_info = {
     .name = TYPE_OT_ALERT,
     .parent = TYPE_SYS_BUS_DEVICE,
     .instance_size = sizeof(OtAlertState),
+    .class_size = sizeof(OtAlertClass),
     .class_init = &ot_alert_class_init,
 };