From c61c852a716766510b139cda2bc9e784a971c74c Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Tue, 24 Sep 2024 11:19:27 -0300 Subject: [PATCH] Exposes the minimum sum threshold detection via Wishbone --- hdl/modules/wb_orbit_intlk/orbit_intlk.vhd | 5 +++ .../wb_orbit_intlk/orbit_intlk_pkg.vhd | 4 +++ hdl/modules/wb_orbit_intlk/wb_orbit_intlk.vhd | 2 ++ .../wbgen/doc/orbit_intlk_regs_wb.html | 35 +++++++++++++++---- .../wb_orbit_intlk/wbgen/orbit_intlk_regs.h | 10 +++--- .../wbgen/wb_orbit_intlk_regs.vhd | 6 ++-- .../wbgen/wb_orbit_intlk_regs.wb | 12 +++++-- .../wbgen/wb_orbit_intlk_regs_pkg.vhd | 9 +++-- hdl/sim/regs/wb_orbit_intlk_regs.vh | 6 ++-- .../regs/wb_orbit_intlk_regs_const_pkg.vhd | 6 ++-- .../orbit_intlk/xwb_orbit_intlk_tb.vhd | 17 ++++++++- 11 files changed, 88 insertions(+), 24 deletions(-) diff --git a/hdl/modules/wb_orbit_intlk/orbit_intlk.vhd b/hdl/modules/wb_orbit_intlk/orbit_intlk.vhd index 5743985d..1e233459 100644 --- a/hdl/modules/wb_orbit_intlk/orbit_intlk.vhd +++ b/hdl/modules/wb_orbit_intlk/orbit_intlk.vhd @@ -181,6 +181,10 @@ port -- conditional to intlk_en_i intlk_ang_o : out std_logic; + -- '1' if decim_us/ds_pos_sum_i > intlk_min_sum_i, '0' otherwise. + -- Clock domain: ref_clk_i + intlk_sum_bigger_any_o : out std_logic; + -- only cleared when intlk_clr_i is asserted intlk_ltc_o : out std_logic; -- conditional to intlk_en_i @@ -423,6 +427,7 @@ begin end if; end process; + intlk_sum_bigger_any_o <= intlk_sum_bigger_any; intlk_sum_bigger_en <= '1' when intlk_min_sum_en_i = '0' else intlk_sum_bigger_any; ----------------------------- diff --git a/hdl/modules/wb_orbit_intlk/orbit_intlk_pkg.vhd b/hdl/modules/wb_orbit_intlk/orbit_intlk_pkg.vhd index cc5be797..368576f9 100644 --- a/hdl/modules/wb_orbit_intlk/orbit_intlk_pkg.vhd +++ b/hdl/modules/wb_orbit_intlk/orbit_intlk_pkg.vhd @@ -191,6 +191,10 @@ package orbit_intlk_pkg is -- conditional to intlk_en_i intlk_ang_o : out std_logic; + -- '1' if decim_us/ds_pos_sum_i > intlk_min_sum_i, '0' otherwise. + -- Clock domain: ref_clk_i + intlk_sum_bigger_any_o : out std_logic; + -- only cleared when intlk_clr_i is asserted intlk_ltc_o : out std_logic; -- conditional to intlk_en_i diff --git a/hdl/modules/wb_orbit_intlk/wb_orbit_intlk.vhd b/hdl/modules/wb_orbit_intlk/wb_orbit_intlk.vhd index bf34144d..e6288049 100644 --- a/hdl/modules/wb_orbit_intlk/wb_orbit_intlk.vhd +++ b/hdl/modules/wb_orbit_intlk/wb_orbit_intlk.vhd @@ -520,6 +520,8 @@ begin intlk_ang_smaller_ltc_o => intlk_ang_smaller_ltc, intlk_ang_smaller_o => intlk_ang_smaller, + intlk_sum_bigger_any_o => regs_in.sts_min_sum_bigger_i, + intlk_ltc_o => intlk_ltc, intlk_o => intlk ); diff --git a/hdl/modules/wb_orbit_intlk/wbgen/doc/orbit_intlk_regs_wb.html b/hdl/modules/wb_orbit_intlk/wbgen/doc/orbit_intlk_regs_wb.html index fd7c4a3b..81417f65 100644 --- a/hdl/modules/wb_orbit_intlk/wbgen/doc/orbit_intlk_regs_wb.html +++ b/hdl/modules/wb_orbit_intlk/wbgen/doc/orbit_intlk_regs_wb.html @@ -1035,10 +1035,27 @@

2. HDL symbol

-orbit_intlk_sts_reserved_i[1:0] +orbit_intlk_sts_min_sum_bigger_i -⇐ +← + + + + + + + + + + + + + +orbit_intlk_sts_reserved_i + + +← @@ -2063,8 +2080,11 @@

3.2. General Status Signals

- -RESERVED[1:0] + +RESERVED + + +MIN_SUM_BIGGER ANG_SMALLER_LTC @@ -2083,9 +2103,6 @@

3.2. General Status Signals

ANG_SMALLER_Y - - - @@ -2373,6 +2390,10 @@

3.2. General Status Signals

[read-only]: Angular Smaller Latched
Angular Smaller Latched
  • +MIN_SUM_BIGGER +[read-only]: Minimum sum threshold detection +
    '1' if the BPM amplitudes sums are bigger than the value specified in min_sum, '0' otherwise. +
  • RESERVED [read-only]: Reserved
    Ignore on write, read as 0's diff --git a/hdl/modules/wb_orbit_intlk/wbgen/orbit_intlk_regs.h b/hdl/modules/wb_orbit_intlk/wbgen/orbit_intlk_regs.h index 142c8afe..9b5408b2 100644 --- a/hdl/modules/wb_orbit_intlk/wbgen/orbit_intlk_regs.h +++ b/hdl/modules/wb_orbit_intlk/wbgen/orbit_intlk_regs.h @@ -3,7 +3,7 @@ * File : orbit_intlk_regs.h * Author : auto-generated by wbgen2 from wb_orbit_intlk_regs.wb - * Created : Mon Oct 25 13:33:06 2021 + * Created : Tue Sep 24 11:12:27 2024 * Standard : ANSI C THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_orbit_intlk_regs.wb @@ -156,11 +156,11 @@ /* definitions for field: Angular Smaller Latched in reg: General Status Signals */ #define ORBIT_INTLK_STS_ANG_SMALLER_LTC WBGEN2_GEN_MASK(29, 1) +/* definitions for field: Minimum sum threshold detection in reg: General Status Signals */ +#define ORBIT_INTLK_STS_MIN_SUM_BIGGER WBGEN2_GEN_MASK(30, 1) + /* definitions for field: Reserved in reg: General Status Signals */ -#define ORBIT_INTLK_STS_RESERVED_MASK WBGEN2_GEN_MASK(30, 2) -#define ORBIT_INTLK_STS_RESERVED_SHIFT 30 -#define ORBIT_INTLK_STS_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 30, 2) -#define ORBIT_INTLK_STS_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 30, 2) +#define ORBIT_INTLK_STS_RESERVED WBGEN2_GEN_MASK(31, 1) /* definitions for register: Minimum sum threshold */ diff --git a/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.vhd b/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.vhd index f3b9b888..936d2ce3 100644 --- a/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.vhd +++ b/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.vhd @@ -3,7 +3,7 @@ --------------------------------------------------------------------------------------- -- File : wb_orbit_intlk_regs.vhd -- Author : auto-generated by wbgen2 from wb_orbit_intlk_regs.wb --- Created : Mon Oct 25 13:33:06 2021 +-- Created : Tue Sep 24 11:12:27 2024 -- Standard : VHDL'87 --------------------------------------------------------------------------------------- -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_orbit_intlk_regs.wb @@ -311,7 +311,8 @@ begin rddata_reg(27) <= regs_i.sts_ang_smaller_any_i; rddata_reg(28) <= regs_i.sts_ang_smaller_i; rddata_reg(29) <= regs_i.sts_ang_smaller_ltc_i; - rddata_reg(31 downto 30) <= regs_i.sts_reserved_i; + rddata_reg(30) <= regs_i.sts_min_sum_bigger_i; + rddata_reg(31) <= regs_i.sts_reserved_i; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "0010" => @@ -526,6 +527,7 @@ begin -- Angular Smaller Any (X/Y) -- Angular Smaller -- Angular Smaller Latched +-- Minimum sum threshold detection -- Reserved -- Minimum Sum Threshold -- asynchronous std_logic_vector register : Minimum Sum Threshold (type RW/RO, fs_clk_i <-> clk_sys_i) diff --git a/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.wb b/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.wb index 52a49962..0bd2d791 100644 --- a/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.wb +++ b/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.wb @@ -360,12 +360,20 @@ peripheral { access_dev = WRITE_ONLY; }; + field { + name = "Minimum sum threshold detection"; + description = "'1' if the BPM amplitudes sums are bigger than the value specified in min_sum, '0' otherwise."; + prefix = "min_sum_bigger"; + type = BIT; + access_bus = READ_ONLY; + access_dev = WRITE_ONLY; + }; + field { name = "Reserved"; description = "Ignore on write, read as 0's"; prefix = "reserved"; - type = SLV; - size = 2; + type = BIT; access_bus = READ_ONLY; access_dev = WRITE_ONLY; }; diff --git a/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs_pkg.vhd b/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs_pkg.vhd index 27579a7d..ca4a24de 100644 --- a/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs_pkg.vhd +++ b/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs_pkg.vhd @@ -3,7 +3,7 @@ --------------------------------------------------------------------------------------- -- File : wb_orbit_intlk_regs_pkg.vhd -- Author : auto-generated by wbgen2 from wb_orbit_intlk_regs.wb --- Created : Mon Oct 25 13:33:06 2021 +-- Created : Tue Sep 24 11:12:27 2024 -- Standard : VHDL'87 --------------------------------------------------------------------------------------- -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_orbit_intlk_regs.wb @@ -51,7 +51,8 @@ package orbit_intlk_wbgen2_pkg is sts_ang_smaller_any_i : std_logic; sts_ang_smaller_i : std_logic; sts_ang_smaller_ltc_i : std_logic; - sts_reserved_i : std_logic_vector(1 downto 0); + sts_min_sum_bigger_i : std_logic; + sts_reserved_i : std_logic; trans_x_diff_i : std_logic_vector(31 downto 0); trans_y_diff_i : std_logic_vector(31 downto 0); ang_x_diff_i : std_logic_vector(31 downto 0); @@ -90,7 +91,8 @@ package orbit_intlk_wbgen2_pkg is sts_ang_smaller_any_i => '0', sts_ang_smaller_i => '0', sts_ang_smaller_ltc_i => '0', - sts_reserved_i => (others => '0'), + sts_min_sum_bigger_i => '0', + sts_reserved_i => '0', trans_x_diff_i => (others => '0'), trans_y_diff_i => (others => '0'), ang_x_diff_i => (others => '0'), @@ -221,6 +223,7 @@ package body orbit_intlk_wbgen2_pkg is tmp.sts_ang_smaller_any_i := f_x_to_zero(left.sts_ang_smaller_any_i) or f_x_to_zero(right.sts_ang_smaller_any_i); tmp.sts_ang_smaller_i := f_x_to_zero(left.sts_ang_smaller_i) or f_x_to_zero(right.sts_ang_smaller_i); tmp.sts_ang_smaller_ltc_i := f_x_to_zero(left.sts_ang_smaller_ltc_i) or f_x_to_zero(right.sts_ang_smaller_ltc_i); + tmp.sts_min_sum_bigger_i := f_x_to_zero(left.sts_min_sum_bigger_i) or f_x_to_zero(right.sts_min_sum_bigger_i); tmp.sts_reserved_i := f_x_to_zero(left.sts_reserved_i) or f_x_to_zero(right.sts_reserved_i); tmp.trans_x_diff_i := f_x_to_zero(left.trans_x_diff_i) or f_x_to_zero(right.trans_x_diff_i); tmp.trans_y_diff_i := f_x_to_zero(left.trans_y_diff_i) or f_x_to_zero(right.trans_y_diff_i); diff --git a/hdl/sim/regs/wb_orbit_intlk_regs.vh b/hdl/sim/regs/wb_orbit_intlk_regs.vh index a22e3db2..4cd42612 100644 --- a/hdl/sim/regs/wb_orbit_intlk_regs.vh +++ b/hdl/sim/regs/wb_orbit_intlk_regs.vh @@ -76,8 +76,10 @@ `define ORBIT_INTLK_STS_ANG_SMALLER 32'h10000000 `define ORBIT_INTLK_STS_ANG_SMALLER_LTC_OFFSET 29 `define ORBIT_INTLK_STS_ANG_SMALLER_LTC 32'h20000000 -`define ORBIT_INTLK_STS_RESERVED_OFFSET 30 -`define ORBIT_INTLK_STS_RESERVED 32'hc0000000 +`define ORBIT_INTLK_STS_MIN_SUM_BIGGER_OFFSET 30 +`define ORBIT_INTLK_STS_MIN_SUM_BIGGER 32'h40000000 +`define ORBIT_INTLK_STS_RESERVED_OFFSET 31 +`define ORBIT_INTLK_STS_RESERVED 32'h80000000 `define ADDR_ORBIT_INTLK_MIN_SUM 6'h8 `define ADDR_ORBIT_INTLK_TRANS_MAX_X 6'hc `define ADDR_ORBIT_INTLK_TRANS_MAX_Y 6'h10 diff --git a/hdl/sim/regs/wb_orbit_intlk_regs_const_pkg.vhd b/hdl/sim/regs/wb_orbit_intlk_regs_const_pkg.vhd index 05c25bb4..0a1c83ef 100644 --- a/hdl/sim/regs/wb_orbit_intlk_regs_const_pkg.vhd +++ b/hdl/sim/regs/wb_orbit_intlk_regs_const_pkg.vhd @@ -81,8 +81,10 @@ package wb_orbit_intlk_regs_const_pkg is constant ORBIT_INTLK_STS_ANG_SMALLER: std_logic_vector(31 downto 0) := x"10000000"; constant ORBIT_INTLK_STS_ANG_SMALLER_LTC_OFFSET: integer := 29; constant ORBIT_INTLK_STS_ANG_SMALLER_LTC: std_logic_vector(31 downto 0) := x"20000000"; - constant ORBIT_INTLK_STS_RESERVED_OFFSET: integer := 30; - constant ORBIT_INTLK_STS_RESERVED: std_logic_vector(31 downto 0) := x"c0000000"; + constant ORBIT_INTLK_STS_MIN_SUM_BIGGER_OFFSET: integer := 30; + constant ORBIT_INTLK_STS_MIN_SUM_BIGGER: std_logic_vector(31 downto 0) := x"40000000"; + constant ORBIT_INTLK_STS_RESERVED_OFFSET: integer := 31; + constant ORBIT_INTLK_STS_RESERVED: std_logic_vector(31 downto 0) := x"80000000"; constant ADDR_ORBIT_INTLK_MIN_SUM: std_logic_vector(31 downto 0) := x"00000008"; constant ADDR_ORBIT_INTLK_TRANS_MAX_X: std_logic_vector(31 downto 0) := x"0000000c"; constant ADDR_ORBIT_INTLK_TRANS_MAX_Y: std_logic_vector(31 downto 0) := x"00000010"; diff --git a/hdl/testbench/orbit_intlk/xwb_orbit_intlk_tb.vhd b/hdl/testbench/orbit_intlk/xwb_orbit_intlk_tb.vhd index 436563f9..b75e9cfc 100644 --- a/hdl/testbench/orbit_intlk/xwb_orbit_intlk_tb.vhd +++ b/hdl/testbench/orbit_intlk/xwb_orbit_intlk_tb.vhd @@ -6,7 +6,7 @@ -- Author : Augusto Fraga Giachero -- Company : CNPEM -- Created : 2024-09-16 --- Last update: 2024-09-23 +-- Last update: 2024-09-25 -- Platform : Simulation -- Standard : VHDL 2008 ------------------------------------------------------------------------------- @@ -210,6 +210,21 @@ architecture sim of xwb_orbit_intlk_tb is ": Wishbone register DID NOT correctly identify a condition." severity failure; + -- Check if the minimum sum detection is correctly reflected on the + -- min_sum_bigger status bit + if signed(test_stimulus.decim_us_pos.sum) >= signed(test_stimulus.intlk_min_sum) or + signed(test_stimulus.decim_ds_pos.sum) >= signed(test_stimulus.intlk_min_sum) then + assert wb_reg(ORBIT_INTLK_STS_MIN_SUM_BIGGER_OFFSET) = '1' + report "Minimum sum threshold not indicated on min_sum_bigger!" & LF & + "Expected '1' got : '0'" + severity failure; + else + assert wb_reg(ORBIT_INTLK_STS_MIN_SUM_BIGGER_OFFSET) = '0' + report "Minimum sum threshold falsely indicated on min_sum_bigger!" & LF & + "Expected '0' got : '1'" + severity failure; + end if; + -- Wait for some time between tests f_wait_cycles(clk, 1); end procedure;