[FIRRTL] Add require and ensure intrinsics #8154
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Add a simple pass that removes all contracts from the IR, treating them as passthroughs. Run the pass in firtool's HW-to-SV pipeline early on to add additional optimization opportunities. ExportVerilog will eventually ignore contracts anyway.
Add the `circt.verif.require` and `circt.verif.ensure` intrinsics as a way to produce the `verif.require` and `verif.ensure` operations from FIRRTL. At a later point we'll probably want to promote the five verif ops `assert`, `assume`, `cover`, `require`, and `ensure` to the FIRRTL spec and merge the functionality of the `circt.verif.assert` intrinsic with the `firrtl.assert` operation. Note that this requires dropping of the clock operand from `verif.require` and `verif.ensure`. This operand was never used, so it feels like a reasonable change. At a later point we might want to merge `verif.clocked_assert` into `verif.assert` by adding clock operands to the verif ops in general.
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Add the
circt.verif.requireandcirct.verif.ensureintrinsics as a way to produce theverif.requireandverif.ensureoperations from FIRRTL. At a later point we'll probably want to promote the five verif opsassert,assume,cover,require, andensureto the FIRRTL spec and merge the functionality of thecirct.verif.assertintrinsic with thefirrtl.assertoperation.Note that this requires dropping of the clock operand from
verif.requireandverif.ensure. This operand was never used, so it feels like a reasonable change. At a later point we might want to mergeverif.clocked_assertintoverif.assertby adding clock operands to the verif ops in general.