[RTGTest] Add integer register type API (#8141)

llvm · Feb 3, 2025 · deb88ba · deb88ba
1 parent 518f3a1
commit deb88ba
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Showing 5 changed files with 37 additions and 2 deletions.
diff --git a/include/circt-c/Dialect/RTGTest.h b/include/circt-c/Dialect/RTGTest.h
@@ -31,6 +31,12 @@ MLIR_CAPI_EXPORTED bool rtgtestTypeIsACPU(MlirType type);
 /// Creates an RTGTest CPU type in the context.
 MLIR_CAPI_EXPORTED MlirType rtgtestCPUTypeGet(MlirContext ctxt);
 
+/// If the type is an RTGTest IntegerRegisterType.
+MLIR_CAPI_EXPORTED bool rtgtestTypeIsAIntegerRegister(MlirType type);
+
+/// Creates an RTGTest IntegerRegisterType in the context.
+MLIR_CAPI_EXPORTED MlirType rtgtestIntegerRegisterTypeGet(MlirContext ctxt);
+
 // Immediates.
 //===----------------------------------------------------------------------===//
 

diff --git a/integration_test/Bindings/Python/dialects/rtg.py b/integration_test/Bindings/Python/dialects/rtg.py
@@ -88,11 +88,13 @@
     labelTy = rtg.LabelType.get()
     setTy = rtg.SetType.get(indexTy)
     bagTy = rtg.BagType.get(indexTy)
+    ireg = rtgtest.IntegerRegisterType.get()
     seq = rtg.SequenceOp('seq')
-    Block.create_at_start(seq.bodyRegion, [sequenceTy, labelTy, setTy, bagTy])
+    Block.create_at_start(seq.bodyRegion,
+                          [sequenceTy, labelTy, setTy, bagTy, ireg])
 
   # CHECK: rtg.sequence @seq
-  # CHECK: (%{{.*}}: !rtg.sequence, %{{.*}}: !rtg.label, %{{.*}}: !rtg.set<index>, %{{.*}}: !rtg.bag<index>):
+  # CHECK: (%{{.*}}: !rtg.sequence, %{{.*}}: !rtg.label, %{{.*}}: !rtg.set<index>, %{{.*}}: !rtg.bag<index>, %{{.*}}: !rtgtest.ireg):
   print(m)
 
 with Context() as ctx, Location.unknown():

diff --git a/lib/Bindings/Python/RTGTestModule.cpp b/lib/Bindings/Python/RTGTestModule.cpp
@@ -30,6 +30,14 @@ void circt::python::populateDialectRTGTestSubmodule(nb::module_ &m) {
           },
           nb::arg("self"), nb::arg("ctxt") = nullptr);
 
+  mlir_type_subclass(m, "IntegerRegisterType", rtgtestTypeIsAIntegerRegister)
+      .def_classmethod(
+          "get",
+          [](nb::object cls, MlirContext ctxt) {
+            return cls(rtgtestIntegerRegisterTypeGet(ctxt));
+          },
+          nb::arg("self"), nb::arg("ctxt") = nullptr);
+
   mlir_type_subclass(m, "Imm12Type", rtgtestTypeIsAImm12)
       .def_classmethod(
           "get",

diff --git a/lib/CAPI/Dialect/RTGTest.cpp b/lib/CAPI/Dialect/RTGTest.cpp
@@ -32,6 +32,14 @@ MlirType rtgtestCPUTypeGet(MlirContext ctxt) {
   return wrap(CPUType::get(unwrap(ctxt)));
 }
 
+bool rtgtestTypeIsAIntegerRegister(MlirType type) {
+  return isa<IntegerRegisterType>(unwrap(type));
+}
+
+MlirType rtgtestIntegerRegisterTypeGet(MlirContext ctxt) {
+  return wrap(IntegerRegisterType::get(unwrap(ctxt)));
+}
+
 // Immediates.
 //===----------------------------------------------------------------------===//
 

diff --git a/test/CAPI/rtgtest.c b/test/CAPI/rtgtest.c
@@ -21,6 +21,16 @@ static void testCPUType(MlirContext ctx) {
   mlirTypeDump(cpuTy);
 }
 
+static void testIntegerRegisterType(MlirContext ctx) {
+  MlirType iregTy = rtgtestIntegerRegisterTypeGet(ctx);
+
+  // CHECK: is_ireg
+  fprintf(stderr,
+          rtgtestTypeIsAIntegerRegister(iregTy) ? "is_ireg\n" : "isnot_ireg\n");
+  // CHECK: !rtgtest.ireg
+  mlirTypeDump(iregTy);
+}
+
 static void testCPUAttr(MlirContext ctx) {
   MlirAttribute cpuAttr = rtgtestCPUAttrGet(ctx, 3);
 
@@ -322,6 +332,7 @@ int main(int argc, char **argv) {
   mlirDialectHandleLoadDialect(mlirGetDialectHandle__rtgtest__(), ctx);
 
   testCPUType(ctx);
+  testIntegerRegisterType(ctx);
   testCPUAttr(ctx);
   testRegisters(ctx);
   testImmediates(ctx);