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Add a simple pass that removes all contracts from the IR, treating them as passthroughs. Run the pass in firtool's HW-to-SV pipeline early on to add additional optimization opportunities. ExportVerilog will eventually ignore contracts anyway.
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//===- StripContracts.cpp -------------------------------------------------===// | ||
// | ||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||
// See https://llvm.org/LICENSE.txt for license information. | ||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
// | ||
//===----------------------------------------------------------------------===// | ||
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#include "circt/Dialect/Verif/VerifOps.h" | ||
#include "circt/Dialect/Verif/VerifPasses.h" | ||
#include "mlir/Pass/Pass.h" | ||
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namespace circt { | ||
namespace verif { | ||
#define GEN_PASS_DEF_STRIPCONTRACTSPASS | ||
#include "circt/Dialect/Verif/Passes.h.inc" | ||
} // namespace verif | ||
} // namespace circt | ||
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using namespace mlir; | ||
using namespace circt; | ||
using namespace verif; | ||
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namespace { | ||
struct StripContractsPass | ||
: public verif::impl::StripContractsPassBase<StripContractsPass> { | ||
void runOnOperation() override { | ||
getOperation()->walk([](ContractOp op) { | ||
op->replaceUsesWithIf(op.getInputs(), [&](OpOperand &operand) { | ||
return operand.getOwner() != op; | ||
}); | ||
// Prevent removal of self-referential contracts that have other users. | ||
// Removing them would result in invalid IR. | ||
for (auto operand : op->getOperands()) | ||
if (operand.getDefiningOp() == op) | ||
for (auto *user : operand.getUsers()) | ||
if (user != op) | ||
return; | ||
op->dropAllReferences(); | ||
op->erase(); | ||
}); | ||
} | ||
}; | ||
} // namespace |
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// RUN: circt-opt --strip-contracts %s | FileCheck %s | ||
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// CHECK-LABEL: func @foo | ||
func.func @foo(%arg0: i42) -> i42 { | ||
// CHECK-NOT: verif.contract | ||
%0 = verif.contract %arg0 : i42 {} | ||
// CHECK: return %arg0 | ||
return %0 : i42 | ||
} | ||
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// CHECK-LABEL: hw.module @bar | ||
hw.module @bar() { | ||
// CHECK-NOT: verif.contract | ||
%0 = verif.contract %1 : i42 {} | ||
%1 = verif.contract %0 : i42 {} | ||
} | ||
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// CHECK-LABEL: hw.module @baz | ||
hw.module @baz(out z: i42) { | ||
// CHECK: [[TMP:%.+]] = verif.contract [[TMP]] | ||
// CHECK: hw.output [[TMP]] | ||
%2 = verif.contract %3 : i42 {} | ||
%3 = verif.contract %2 : i42 {} | ||
hw.output %3 : i42 | ||
} |