diff --git a/include/circt-c/Dialect/RTGTest.h b/include/circt-c/Dialect/RTGTest.h index 5bc68ea0be06..4ee336433f7c 100644 --- a/include/circt-c/Dialect/RTGTest.h +++ b/include/circt-c/Dialect/RTGTest.h @@ -40,6 +40,12 @@ MLIR_CAPI_EXPORTED MlirType rtgtestIntegerRegisterTypeGet(MlirContext ctxt); // Immediates. //===----------------------------------------------------------------------===// +/// If the type is an RTGTest Imm5Type. +MLIR_CAPI_EXPORTED bool rtgtestTypeIsAImm5(MlirType type); + +/// Creates an RTGTest Imm5 type in the context. +MLIR_CAPI_EXPORTED MlirType rtgtestImm5TypeGet(MlirContext ctxt); + /// If the type is an RTGTest Imm12Type. MLIR_CAPI_EXPORTED bool rtgtestTypeIsAImm12(MlirType type); @@ -276,6 +282,16 @@ MLIR_CAPI_EXPORTED MlirAttribute rtgtestRegT6AttrGet(MlirContext ctxt); // Immediates. //===----------------------------------------------------------------------===// +/// If the attribute is an RTGTest Imm5Attr. +MLIR_CAPI_EXPORTED bool rtgtestAttrIsAImm5(MlirAttribute attr); + +/// Creates an RTGTest Imm5 attribute in the context. +MLIR_CAPI_EXPORTED MlirAttribute rtgtestImm5AttrGet(MlirContext ctxt, + unsigned value); + +/// Returns the value represented by the Imm5 attribute. +MLIR_CAPI_EXPORTED unsigned rtgtestImm5AttrGetValue(MlirAttribute attr); + /// If the attribute is an RTGTest Imm12Attr. MLIR_CAPI_EXPORTED bool rtgtestAttrIsAImm12(MlirAttribute attr); diff --git a/include/circt/Dialect/RTGTest/IR/RTGTestAttributes.td b/include/circt/Dialect/RTGTest/IR/RTGTestAttributes.td index c61ae8c7ac48..5f0fffc7312a 100644 --- a/include/circt/Dialect/RTGTest/IR/RTGTestAttributes.td +++ b/include/circt/Dialect/RTGTest/IR/RTGTestAttributes.td @@ -71,6 +71,7 @@ class ImmediateAttrBase : RTGTestAttrDef<"Imm" # width, [ let genVerifyDecl = 1; } +def Imm5 : ImmediateAttrBase<5>; def Imm12 : ImmediateAttrBase<12>; def Imm13 : ImmediateAttrBase<13>; def Imm21 : ImmediateAttrBase<21>; diff --git a/include/circt/Dialect/RTGTest/IR/RTGTestOps.td b/include/circt/Dialect/RTGTest/IR/RTGTestOps.td index 1d92794f9e79..939b42d7f314 100644 --- a/include/circt/Dialect/RTGTest/IR/RTGTestOps.td +++ b/include/circt/Dialect/RTGTest/IR/RTGTestOps.td @@ -48,7 +48,7 @@ def ImmediateOp : RTGTestOp<"immediate", [ ]> { let summary = "declare an immediate value"; - let arguments = (ins AnyAttrOf<[Imm12, Imm13, Imm21, Imm32]>:$imm); + let arguments = (ins AnyAttrOf<[Imm5, Imm12, Imm13, Imm21, Imm32]>:$imm); let results = (outs AnyType:$result); let assemblyFormat = "$imm attr-dict"; @@ -98,7 +98,8 @@ class InstFormatIOpBase << cast(adaptor.getRd()) .getRegisterAssembly() << ", " - << cast(adaptor.getImm()).getValue() + // The assembler only accepts signed values here. + << cast(adaptor.getImm()).getAPInt().getSExtValue() << "(" << cast(adaptor.getRs()) .getRegisterAssembly() @@ -182,6 +183,7 @@ class InstFormatBOpBase return; } + // The assembler is fine with unsigned and signed values here. os << cast(adaptor.getImm()).getValue(); } }]; @@ -266,7 +268,8 @@ class InstFormatSOpBase << cast(adaptor.getRs1()) .getRegisterAssembly() << ", " - << cast(adaptor.getImm()).getValue() + // The assembler only accepts signed values here. + << cast(adaptor.getImm()).getAPInt().getSExtValue() << "(" << cast(adaptor.getRs2()) .getRegisterAssembly() @@ -275,8 +278,192 @@ class InstFormatSOpBase }]; } +class InstFormatUOpBase + : RTGTestOp<"rv32i." # mnemonic, [InstructionOpAdaptor]> { + + let arguments = (ins IntegerRegisterType:$rd, + AnyTypeOf<[Imm32Type, LabelType]>:$imm); + + let assemblyFormat = "$rd `,` $imm `:` type($imm) attr-dict"; + + let extraClassDefinition = [{ + void $cppClass::printInstructionBinary(llvm::raw_ostream &os, + FoldAdaptor adaptor) { + assert (isa(adaptor.getImm()) && + "binary of labels not supported"); + + auto rd = cast(adaptor.getRd()); + auto imm = cast(adaptor.getImm()).getAPInt(); + + auto binary = imm.extractBits(20, 12) + .concat(llvm::APInt(5, rd.getClassIndex())) + .concat(llvm::APInt(7, }] # opcode7 # [{)); + + SmallVector str; + binary.toStringUnsigned(str, 16); + os << str; + } + + void $cppClass::printInstructionAssembly(llvm::raw_ostream &os, + FoldAdaptor adaptor) { + os << getOperationName().rsplit('.').second + << " " + << cast(adaptor.getRd()) + .getRegisterAssembly() + << ", "; + + if (auto label = dyn_cast(adaptor.getImm())) { + os << label.getValue(); + return; + } + + // The assembler wants an unsigned value here. + os << cast(adaptor.getImm()).getValue(); + } + }]; +} + +class InstFormatJOpBase + : RTGTestOp<"rv32i." # mnemonic, [InstructionOpAdaptor]> { + + let arguments = (ins IntegerRegisterType:$rd, + AnyTypeOf<[Imm21Type, LabelType]>:$imm); + + let assemblyFormat = "$rd `,` $imm `:` type($imm) attr-dict"; + + let extraClassDefinition = [{ + void $cppClass::printInstructionBinary(llvm::raw_ostream &os, + FoldAdaptor adaptor) { + assert (isa(adaptor.getImm()) && + "binary of labels not supported"); + + auto rd = cast(adaptor.getRd()); + auto imm = cast(adaptor.getImm()).getAPInt(); + + auto binary = imm.extractBits(1, 20) + .concat(imm.extractBits(10, 1)) + .concat(imm.extractBits(1, 1)) + .concat(imm.extractBits(8, 12)) + .concat(llvm::APInt(5, rd.getClassIndex())) + .concat(llvm::APInt(7, }] # opcode7 # [{)); + + SmallVector str; + binary.toStringUnsigned(str, 16); + os << str; + } + + void $cppClass::printInstructionAssembly(llvm::raw_ostream &os, + FoldAdaptor adaptor) { + os << getOperationName().rsplit('.').second + << " " + << cast(adaptor.getRd()) + .getRegisterAssembly() + << ", "; + + if (auto label = dyn_cast(adaptor.getImm())) { + os << label.getValue(); + return; + } + + // The assembler is fine with signed and unsigned values here. + os << cast(adaptor.getImm()).getAPInt().getSExtValue(); + } + }]; +} + +class InstFormatIAOpBase + : RTGTestOp<"rv32i." # mnemonic, [InstructionOpAdaptor]> { + + let arguments = (ins IntegerRegisterType:$rd, + IntegerRegisterType:$rs, + Imm12Type:$imm); + + let assemblyFormat = "$rd `,` $rs `,` $imm attr-dict"; + + let extraClassDefinition = [{ + void $cppClass::printInstructionBinary(llvm::raw_ostream &os, + FoldAdaptor adaptor) { + auto rd = cast(adaptor.getRd()); + auto rs = cast(adaptor.getRs()); + auto imm = cast(adaptor.getImm()).getAPInt(); + + auto binary = imm + .concat(llvm::APInt(5, rs.getClassIndex())) + .concat(llvm::APInt(3, }] # funct3 # [{)) + .concat(llvm::APInt(5, rd.getClassIndex())) + .concat(llvm::APInt(7, }] # opcode7 # [{)); + + SmallVector str; + binary.toStringUnsigned(str, 16); + os << str; + } + + void $cppClass::printInstructionAssembly(llvm::raw_ostream &os, + FoldAdaptor adaptor) { + os << getOperationName().rsplit('.').second + << " " + << cast(adaptor.getRd()) + .getRegisterAssembly() + << ", " + << cast(adaptor.getRs()) + .getRegisterAssembly() + << ", " + // The assembler only accepts signed values here. + << cast(adaptor.getImm()).getAPInt().getSExtValue(); + } + }]; +} + +class InstFormatShiftOpBase + : RTGTestOp<"rv32i." # mnemonic, [InstructionOpAdaptor]> { + + let arguments = (ins IntegerRegisterType:$rd, + IntegerRegisterType:$rs, + Imm5Type:$imm); + + let assemblyFormat = "$rd `,` $rs `,` $imm attr-dict"; + + let extraClassDefinition = [{ + void $cppClass::printInstructionBinary(llvm::raw_ostream &os, + FoldAdaptor adaptor) { + auto rd = cast(adaptor.getRd()); + auto rs = cast(adaptor.getRs()); + auto imm = cast(adaptor.getImm()).getAPInt(); + + auto binary = llvm::APInt(7, }] # funct7 # [{) + .concat(imm.extractBits(5, 0)) + .concat(llvm::APInt(5, rs.getClassIndex())) + .concat(llvm::APInt(3, }] # funct3 # [{)) + .concat(llvm::APInt(5, rd.getClassIndex())) + .concat(llvm::APInt(7, }] # opcode7 # [{)); + + SmallVector str; + binary.toStringUnsigned(str, 16); + os << str; + } + + void $cppClass::printInstructionAssembly(llvm::raw_ostream &os, + FoldAdaptor adaptor) { + os << getOperationName().rsplit('.').second + << " " + << cast(adaptor.getRd()) + .getRegisterAssembly() + << ", " + << cast(adaptor.getRs()) + .getRegisterAssembly() + << ", " + // The assembler only accepts an unsigned value here. + << cast(adaptor.getImm()).getValue(); + } + }]; +} + //===- Instructions -------------------------------------------------------===// +def RV32I_LUI : InstFormatUOpBase<"lui", 0b0110111>; +def RV32I_AUIPC : InstFormatUOpBase<"auipc", 0b0010111>; +def RV32I_JAL : InstFormatJOpBase<"jal", 0b1101111>; def RV32I_JALROp : InstFormatIOpBase<"jalr", 0b1100111, 0b000>; def RV32I_BEQ : InstFormatBOpBase<"beq", 0b1100011, 0b000>; @@ -296,6 +483,17 @@ def RV32I_SB : InstFormatSOpBase<"sb", 0b0100011, 0b000>; def RV32I_SH : InstFormatSOpBase<"sh", 0b0100011, 0b001>; def RV32I_SW : InstFormatSOpBase<"sw", 0b0100011, 0b010>; +def RV32I_ADDI : InstFormatIAOpBase<"addi", 0b0010011, 0b000>; +def RV32I_SLTI : InstFormatIAOpBase<"slti", 0b0010011, 0b010>; +def RV32I_SLTIU : InstFormatIAOpBase<"sltiu", 0b0010011, 0b011>; +def RV32I_XORI : InstFormatIAOpBase<"xori", 0b0010011, 0b100>; +def RV32I_ORI : InstFormatIAOpBase<"ori", 0b0010011, 0b110>; +def RV32I_ANDI : InstFormatIAOpBase<"andi", 0b0010011, 0b111>; + +def RV32I_SLLI : InstFormatShiftOpBase<"slli", 0b0010011, 0b001, 0b0000000>; +def RV32I_SRLI : InstFormatShiftOpBase<"srli", 0b0010011, 0b101, 0b0000000>; +def RV32I_SRAI : InstFormatShiftOpBase<"srai", 0b0010011, 0b101, 0b0100000>; + def RV32I_ADD : InstFormatROpBase<"add", 0b110011, 0b000, 0b0000000>; def RV32I_SUB : InstFormatROpBase<"sub", 0b110011, 0b000, 0b0100000>; def RV32I_SLL : InstFormatROpBase<"sll", 0b110011, 0b001, 0b0000000>; diff --git a/include/circt/Dialect/RTGTest/IR/RTGTestTypes.td b/include/circt/Dialect/RTGTest/IR/RTGTestTypes.td index db828d18986a..12ede9cdb0a7 100644 --- a/include/circt/Dialect/RTGTest/IR/RTGTestTypes.td +++ b/include/circt/Dialect/RTGTest/IR/RTGTestTypes.td @@ -38,6 +38,7 @@ class ImmTypeBase : TypeDef { let mnemonic = "imm" # width; } +def Imm5Type : ImmTypeBase<5>; def Imm12Type : ImmTypeBase<12>; def Imm13Type : ImmTypeBase<13>; def Imm21Type : ImmTypeBase<21>; diff --git a/integration_test/Bindings/Python/dialects/rtg.py b/integration_test/Bindings/Python/dialects/rtg.py index d88ae1f1def8..04cdb7719148 100644 --- a/integration_test/Bindings/Python/dialects/rtg.py +++ b/integration_test/Bindings/Python/dialects/rtg.py @@ -172,6 +172,8 @@ circt.register_dialects(ctx) m = Module.create() with InsertionPoint(m.body): + # CHECK: rtgtest.immediate #rtgtest.imm5<3> : !rtgtest.imm5 + rtgtest.ImmediateOp(rtgtest.Imm5Attr.get(3)) # CHECK: rtgtest.immediate #rtgtest.imm12<3> : !rtgtest.imm12 rtgtest.ImmediateOp(rtgtest.Imm12Attr.get(3)) # CHECK: rtgtest.immediate #rtgtest.imm13<3> : !rtgtest.imm13 diff --git a/lib/Bindings/Python/RTGTestModule.cpp b/lib/Bindings/Python/RTGTestModule.cpp index 687114fa639c..a30cf725bc6f 100644 --- a/lib/Bindings/Python/RTGTestModule.cpp +++ b/lib/Bindings/Python/RTGTestModule.cpp @@ -38,6 +38,14 @@ void circt::python::populateDialectRTGTestSubmodule(nb::module_ &m) { }, nb::arg("self"), nb::arg("ctxt") = nullptr); + mlir_type_subclass(m, "Imm5Type", rtgtestTypeIsAImm5) + .def_classmethod( + "get", + [](nb::object cls, MlirContext ctxt) { + return cls(rtgtestImm5TypeGet(ctxt)); + }, + nb::arg("self"), nb::arg("ctxt") = nullptr); + mlir_type_subclass(m, "Imm12Type", rtgtestTypeIsAImm12) .def_classmethod( "get", @@ -336,6 +344,17 @@ void circt::python::populateDialectRTGTestSubmodule(nb::module_ &m) { }, nb::arg("self"), nb::arg("ctxt") = nullptr); + mlir_attribute_subclass(m, "Imm5Attr", rtgtestAttrIsAImm5) + .def_classmethod( + "get", + [](nb::object cls, unsigned value, MlirContext ctxt) { + return cls(rtgtestImm5AttrGet(ctxt, value)); + }, + nb::arg("self"), nb::arg("value"), nb::arg("ctxt") = nullptr) + .def_property_readonly("value", [](MlirAttribute self) { + return rtgtestImm5AttrGetValue(self); + }); + mlir_attribute_subclass(m, "Imm12Attr", rtgtestAttrIsAImm12) .def_classmethod( "get", diff --git a/lib/CAPI/Dialect/RTGTest.cpp b/lib/CAPI/Dialect/RTGTest.cpp index e149e1a3b2c4..27cfe8daaba1 100644 --- a/lib/CAPI/Dialect/RTGTest.cpp +++ b/lib/CAPI/Dialect/RTGTest.cpp @@ -43,6 +43,12 @@ MlirType rtgtestIntegerRegisterTypeGet(MlirContext ctxt) { // Immediates. //===----------------------------------------------------------------------===// +bool rtgtestTypeIsAImm5(MlirType type) { return isa(unwrap(type)); } + +MlirType rtgtestImm5TypeGet(MlirContext ctxt) { + return wrap(Imm5Type::get(unwrap(ctxt))); +} + bool rtgtestTypeIsAImm12(MlirType type) { return isa(unwrap(type)); } MlirType rtgtestImm12TypeGet(MlirContext ctxt) { @@ -345,6 +351,18 @@ MlirAttribute rtgtestRegT6AttrGet(MlirContext ctxt) { // Immediates. //===----------------------------------------------------------------------===// +bool rtgtestAttrIsAImm5(MlirAttribute attr) { + return isa(unwrap(attr)); +} + +MlirAttribute rtgtestImm5AttrGet(MlirContext ctxt, unsigned value) { + return wrap(Imm5Attr::get(unwrap(ctxt), value)); +} + +unsigned rtgtestImm5AttrGetValue(MlirAttribute attr) { + return cast(unwrap(attr)).getValue(); +} + bool rtgtestAttrIsAImm12(MlirAttribute attr) { return isa(unwrap(attr)); } diff --git a/test/CAPI/rtgtest.c b/test/CAPI/rtgtest.c index 6a60fb076122..987c8273af02 100644 --- a/test/CAPI/rtgtest.c +++ b/test/CAPI/rtgtest.c @@ -271,6 +271,12 @@ static void testRegisters(MlirContext ctx) { } static void testImmediates(MlirContext ctx) { + MlirType imm5Type = rtgtestImm5TypeGet(ctx); + // CHECK: is_imm5 + fprintf(stderr, rtgtestTypeIsAImm5(imm5Type) ? "is_imm5\n" : "isnot_imm5\n"); + // CHECK: !rtgtest.imm5 + mlirTypeDump(imm5Type); + MlirType imm12Type = rtgtestImm12TypeGet(ctx); // CHECK: is_imm12 fprintf(stderr, @@ -299,6 +305,14 @@ static void testImmediates(MlirContext ctx) { // CHECK: !rtgtest.imm32 mlirTypeDump(imm32Type); + MlirAttribute imm5Attr = rtgtestImm5AttrGet(ctx, 3); + // CHECK: is_imm5 + fprintf(stderr, rtgtestAttrIsAImm5(imm5Attr) ? "is_imm5\n" : "isnot_imm5\n"); + // CHECK: 3 + fprintf(stderr, "%u\n", rtgtestImm5AttrGetValue(imm5Attr)); + // CHECK: #rtgtest.imm5<3> + mlirAttributeDump(imm5Attr); + MlirAttribute imm12Attr = rtgtestImm12AttrGet(ctx, 3); // CHECK: is_imm12 fprintf(stderr, diff --git a/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-labels.mlir b/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-labels.mlir index 14f4bc7463ca..3a3f3f6edbd7 100644 --- a/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-labels.mlir +++ b/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-labels.mlir @@ -27,6 +27,12 @@ rtg.test @test0 : !rtg.dict<> { rtgtest.rv32i.bltu %rd, %rs, %label : !rtg.label // CHECK-NEXT: bgeu ra, s0, label_name rtgtest.rv32i.bgeu %rd, %rs, %label : !rtg.label + // CHECK-NEXT: lui ra, label_name + rtgtest.rv32i.lui %rd, %label : !rtg.label + // CHECK-NEXT: auipc ra, label_name + rtgtest.rv32i.auipc %rd, %label : !rtg.label + // CHECK-NEXT: jal ra, label_name + rtgtest.rv32i.jal %rd, %label : !rtg.label } // CHECK-EMPTY: diff --git a/test/Dialect/RTG/Transform/emit-rtg-isa-assembly.mlir b/test/Dialect/RTG/Transform/emit-rtg-isa-assembly.mlir index c89665bad01f..ee4e32ed17b3 100644 --- a/test/Dialect/RTG/Transform/emit-rtg-isa-assembly.mlir +++ b/test/Dialect/RTG/Transform/emit-rtg-isa-assembly.mlir @@ -10,12 +10,16 @@ rtg.test @test0 : !rtg.dict<> { %rd = rtg.fixed_reg #rtgtest.ra %rs = rtg.fixed_reg #rtgtest.s0 %imm = rtgtest.immediate #rtgtest.imm12<0> + %imm5 = rtgtest.immediate #rtgtest.imm5<31> + %imm21 = rtgtest.immediate #rtgtest.imm21<0> + %imm32 = rtgtest.immediate #rtgtest.imm32<0> + %neg_imm = rtgtest.immediate #rtgtest.imm12<4080> %imm13 = rtgtest.immediate #rtgtest.imm13<6144> - // CHECK-ALLOWED-NEXT: jalr ra, 0(s0) - // CHECK-NEXT: # jalr ra, 0(s0) - // CHECK-NEXT: .word 0x400E7 - rtgtest.rv32i.jalr %rd, %rs, %imm + // CHECK-ALLOWED-NEXT: jalr ra, -16(s0) + // CHECK-NEXT: # jalr ra, -16(s0) + // CHECK-NEXT: .word 0xFF0400E7 + rtgtest.rv32i.jalr %rd, %rs, %neg_imm // CHECK-ALLOWED-NEXT: lb ra, 0(s0) // CHECK-NEXT: # lb ra, 0(s0) @@ -132,10 +136,10 @@ rtg.test @test0 : !rtg.dict<> { // CHECK-NEXT: .word 0x8470B3 rtgtest.rv32i.and %rd, %rs, %rs - // CHECK-ALLOWED-NEXT: sb ra, 0(s0) - // CHECK-NEXT: # sb ra, 0(s0) - // CHECK-NEXT: .word 0x808023 - rtgtest.rv32i.sb %rd, %rs, %imm + // CHECK-ALLOWED-NEXT: sb ra, -16(s0) + // CHECK-NEXT: # sb ra, -16(s0) + // CHECK-NEXT: .word 0xFE808823 + rtgtest.rv32i.sb %rd, %rs, %neg_imm // CHECK-ALLOWED-NEXT: sh ra, 0(s0) // CHECK-NEXT: # sh ra, 0(s0) @@ -146,6 +150,66 @@ rtg.test @test0 : !rtg.dict<> { // CHECK-NEXT: # sw ra, 0(s0) // CHECK-NEXT: .word 0x80A023 rtgtest.rv32i.sw %rd, %rs, %imm + + // CHECK-ALLOWED-NEXT: lui ra, 0 + // CHECK-NEXT: # lui ra, 0 + // CHECK-NEXT: .word 0xB7 + rtgtest.rv32i.lui %rd, %imm32 : !rtgtest.imm32 + + // CHECK-ALLOWED-NEXT: auipc ra, 0 + // CHECK-NEXT: # auipc ra, 0 + // CHECK-NEXT: .word 0x97 + rtgtest.rv32i.auipc %rd, %imm32 : !rtgtest.imm32 + + // CHECK-ALLOWED-NEXT: jal ra, 0 + // CHECK-NEXT: # jal ra, 0 + // CHECK-NEXT: .word 0xEF + rtgtest.rv32i.jal %rd, %imm21 : !rtgtest.imm21 + + // CHECK-ALLOWED-NEXT: addi ra, s0, -16 + // CHECK-NEXT: # addi ra, s0, -16 + // CHECK-NEXT: .word 0xFF040093 + rtgtest.rv32i.addi %rd, %rs, %neg_imm + + // CHECK-ALLOWED-NEXT: slti ra, s0, 0 + // CHECK-NEXT: # slti ra, s0, 0 + // CHECK-NEXT: .word 0x42093 + rtgtest.rv32i.slti %rd, %rs, %imm + + // CHECK-ALLOWED-NEXT: sltiu ra, s0, 0 + // CHECK-NEXT: # sltiu ra, s0, 0 + // CHECK-NEXT: .word 0x43093 + rtgtest.rv32i.sltiu %rd, %rs, %imm + + // CHECK-ALLOWED-NEXT: xori ra, s0, 0 + // CHECK-NEXT: # xori ra, s0, 0 + // CHECK-NEXT: .word 0x44093 + rtgtest.rv32i.xori %rd, %rs, %imm + + // CHECK-ALLOWED-NEXT: ori ra, s0, 0 + // CHECK-NEXT: # ori ra, s0, 0 + // CHECK-NEXT: .word 0x46093 + rtgtest.rv32i.ori %rd, %rs, %imm + + // CHECK-ALLOWED-NEXT: andi ra, s0, 0 + // CHECK-NEXT: # andi ra, s0, 0 + // CHECK-NEXT: .word 0x47093 + rtgtest.rv32i.andi %rd, %rs, %imm + + // CHECK-ALLOWED-NEXT: slli ra, s0, 31 + // CHECK-NEXT: # slli ra, s0, 31 + // CHECK-NEXT: .word 0x1F41093 + rtgtest.rv32i.slli %rd, %rs, %imm5 + + // CHECK-ALLOWED-NEXT: srli ra, s0, 31 + // CHECK-NEXT: # srli ra, s0, 31 + // CHECK-NEXT: .word 0x1F45093 + rtgtest.rv32i.srli %rd, %rs, %imm5 + + // CHECK-ALLOWED-NEXT: srai ra, s0, 31 + // CHECK-NEXT: # srai ra, s0, 31 + // CHECK-NEXT: .word 0x41F45093 + rtgtest.rv32i.srai %rd, %rs, %imm5 } // CHECK-EMPTY: diff --git a/test/Dialect/RTG/Transform/unsupported-instr.txt b/test/Dialect/RTG/Transform/unsupported-instr.txt index cf64e5fb8a59..3e95c875b9e0 100644 --- a/test/Dialect/RTG/Transform/unsupported-instr.txt +++ b/test/Dialect/RTG/Transform/unsupported-instr.txt @@ -1 +1 @@ -rtgtest.rv32i.jalr,rtgtest.rv32i.lb,rtgtest.rv32i.lh,rtgtest.rv32i.lw,rtgtest.rv32i.lbu,rtgtest.rv32i.lhu,rtgtest.rv32i.beq,rtgtest.rv32i.bne,rtgtest.rv32i.blt,rtgtest.rv32i.bge,rtgtest.rv32i.bltu,rtgtest.rv32i.bgeu,rtgtest.rv32i.add,rtgtest.rv32i.sub,rtgtest.rv32i.sll,rtgtest.rv32i.slt,rtgtest.rv32i.sltu,rtgtest.rv32i.xor,rtgtest.rv32i.srl,rtgtest.rv32i.sra,rtgtest.rv32i.or,rtgtest.rv32i.and,rtgtest.rv32i.sb,rtgtest.rv32i.sh,rtgtest.rv32i.sw +rtgtest.rv32i.jalr,rtgtest.rv32i.lb,rtgtest.rv32i.lh,rtgtest.rv32i.lw,rtgtest.rv32i.lbu,rtgtest.rv32i.lhu,rtgtest.rv32i.beq,rtgtest.rv32i.bne,rtgtest.rv32i.blt,rtgtest.rv32i.bge,rtgtest.rv32i.bltu,rtgtest.rv32i.bgeu,rtgtest.rv32i.add,rtgtest.rv32i.sub,rtgtest.rv32i.sll,rtgtest.rv32i.slt,rtgtest.rv32i.sltu,rtgtest.rv32i.xor,rtgtest.rv32i.srl,rtgtest.rv32i.sra,rtgtest.rv32i.or,rtgtest.rv32i.and,rtgtest.rv32i.sb,rtgtest.rv32i.sh,rtgtest.rv32i.sw,rtgtest.rv32i.lui,rtgtest.rv32i.auipc,rtgtest.rv32i.jal,rtgtest.rv32i.addi,rtgtest.rv32i.slti,rtgtest.rv32i.sltiu,rtgtest.rv32i.xori,rtgtest.rv32i.ori,rtgtest.rv32i.andi,rtgtest.rv32i.slli,rtgtest.rv32i.srli,rtgtest.rv32i.srai diff --git a/test/Dialect/RTGTest/IR/basic.mlir b/test/Dialect/RTGTest/IR/basic.mlir index 8c918d581790..c081285cfe14 100644 --- a/test/Dialect/RTGTest/IR/basic.mlir +++ b/test/Dialect/RTGTest/IR/basic.mlir @@ -88,6 +88,8 @@ rtg.test @registers : !rtg.dict { // CHECK-LABEL: @immediates rtg.test @immediates : !rtg.dict<> { + // CHECK: rtgtest.immediate #rtgtest.imm5<3> : !rtgtest.imm5 + rtgtest.immediate #rtgtest.imm5<3> : !rtgtest.imm5 // CHECK: rtgtest.immediate #rtgtest.imm12<3> : !rtgtest.imm12 rtgtest.immediate #rtgtest.imm12<3> : !rtgtest.imm12 // CHECK: rtgtest.immediate #rtgtest.imm13<3> : !rtgtest.imm13 @@ -99,9 +101,9 @@ rtg.test @immediates : !rtg.dict<> { } // CHECK-LABEL: @instructions -rtg.test @instructions : !rtg.dict { -// CHECK: ([[IMM:%.+]]: !rtgtest.imm12, [[IMM13:%.+]]: !rtgtest.imm13, [[LABEL:%.+]]: !rtg.label, [[RD:%.+]]: !rtgtest.ireg, [[RS:%.+]]: !rtgtest.ireg) -^bb0(%imm: !rtgtest.imm12, %imm13: !rtgtest.imm13, %label: !rtg.label, %rd: !rtgtest.ireg, %rs: !rtgtest.ireg): +rtg.test @instructions : !rtg.dict { +// CHECK: ([[IMM:%.+]]: !rtgtest.imm12, [[IMM13:%.+]]: !rtgtest.imm13, [[IMM21:%.+]]: !rtgtest.imm21, [[IMM32:%.+]]: !rtgtest.imm32, [[IMM5:%.+]]: !rtgtest.imm5, [[LABEL:%.+]]: !rtg.label, [[RD:%.+]]: !rtgtest.ireg, [[RS:%.+]]: !rtgtest.ireg) +^bb0(%imm: !rtgtest.imm12, %imm13: !rtgtest.imm13, %imm21: !rtgtest.imm21, %imm32: !rtgtest.imm32, %imm5: !rtgtest.imm5, %label: !rtg.label, %rd: !rtgtest.ireg, %rs: !rtgtest.ireg): // CHECK: rtgtest.rv32i.jalr [[RD]], [[RS]], [[IMM]] rtgtest.rv32i.jalr %rd, %rs, %imm // CHECK: rtgtest.rv32i.lb [[RD]], [[RS]], [[IMM]] @@ -170,6 +172,40 @@ rtg.test @instructions : !rtg.dict