[circt-verilog] Fix negative Rest timing

In the pass timing summary there is usually a negative amount for Rest which is the result of measuring the verilog parsing and preprocessing twice
llvm · Feb 3, 2025 · 0adc39b · 0adc39b
1 parent 5aa1cc3
commit 0adc39b
Showing 1 changed file with 0 additions and 2 deletions.
diff --git a/tools/circt-verilog/circt-verilog.cpp b/tools/circt-verilog/circt-verilog.cpp
@@ -363,8 +363,6 @@ static LogicalResult executeWithSources(MLIRContext *context,
   OwningOpRef<ModuleOp> module;
   switch (opts.format) {
   case Format::SV: {
-    auto parserTimer = ts.nest("SystemVerilog Parser");
-
     // If the user requested for the files to be only preprocessed, do so and
     // print the results to the configured output file.
     if (opts.loweringMode == LoweringMode::OnlyPreprocess) {