[feature] Adding SystemVerilog support #2

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4 of 5 tasks

canesche opened this issue Jun 4, 2024 · 2 comments

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canesche commented Jun 4, 2024 •

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Tasks;

add SystemVerilog simulator
add circuit print
add stats of the circuit (number of wires, regs, memory, ...)
add waveform
add an example of Google Colab usage: link

canesche added the enhancement label

canesche self-assigned this

pe8sutd commented Jun 6, 2024

great to have SystemVerilog!

pe8sutd commented Nov 5, 2024

Can CAD4u install locally using Anaconda or Conda? thanks.

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