forked from OlmerAod/ADC_Interface
-
Notifications
You must be signed in to change notification settings - Fork 0
/
adc_interface.vt
110 lines (95 loc) · 3.03 KB
/
adc_interface.vt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
`timescale 1 ps/ 1 ps
module adc_interface_vlg_tst();
// constants
// general purpose registers
reg [3:0] SPI_counter = 15;
reg [15:0] data_bus_in_testreg = 0;
reg [15:0] data_bus_out_testreg = 0;
reg [15:0] Din_testvect = 0;
reg [12:0] test_number_counter = 1;
reg [12:0] test_fails_counter = 0;
reg terminate_sim = 0;
// test vector input registers
reg ADC_Dout;
reg clk;
reg [15:0] data_bus_in;
reg reset;
reg transfer_req;
// wires
wire ADC_Din;
wire CS;
wire SCLK;
wire [15:0] data_bus_out;
wire ready;
wire [12:0] tests_number = 1000; // Number of tests to run.
adc_interface i1 (
// port map - connection between master ports and signals/registers
.ADC_Din(ADC_Din),
.ADC_Dout(ADC_Dout),
.CS(CS),
.SCLK(SCLK),
.clk(clk),
.data_bus_in(data_bus_in),
.data_bus_out(data_bus_out),
.ready(ready),
.reset(reset),
.transfer_req(transfer_req)
);
initial
begin
// code that executes only once
clk = 0;
ADC_Dout = 0;
data_bus_in = 0;
transfer_req = 0;
reset = 1; // reset the interface module before tests
#5 reset = 0;
$display("Running testbench");
end
always
begin
#5 clk = !clk; // clk generation
end
always@(posedge ready)
begin
if(Din_testvect == data_bus_in_testreg)
$display("%d: bus -> Din test OK, sent and received: %b", test_number_counter, data_bus_in_testreg);
else
begin
test_fails_counter = test_fails_counter + 1;
$display("%d: bus -> Din test FAIL, sent: %b received: %b at %d", test_number_counter, data_bus_in_testreg, Din_testvect, $time);
end
if(data_bus_out == data_bus_out_testreg)
$display("%d: Dout -> bus test OK, sent and received: %b",test_number_counter, data_bus_out_testreg);
else
begin
test_fails_counter = test_fails_counter + 1;
$display("%d: Dout -> bus test FAIL, sent: %b received: %b at %d",test_number_counter, data_bus_out_testreg, data_bus_out, $time);
end
data_bus_in_testreg = $random;
data_bus_out_testreg = $random;
data_bus_out_testreg[15] = 0;
SPI_counter = 15;
#1
transfer_req = 1;
data_bus_in = data_bus_in_testreg;
#10
transfer_req = 0;
data_bus_in = 0;
if (test_number_counter == tests_number)
begin
$display("Testbench finished. Tests done: %d. Failed data transfers: %d.",test_number_counter, test_fails_counter);
#5 $stop;
end
test_number_counter = test_number_counter + 1;
end
always@(negedge CS or negedge SCLK)
begin
Din_testvect[SPI_counter] = ADC_Din;
end
always@(negedge SCLK)
begin
SPI_counter = SPI_counter - 1;
ADC_Dout = data_bus_out_testreg[SPI_counter];
end
endmodule