| title | author | layout |
|---|---|---|
Introduction to ASIC Design |
Kevin Kiningham |
default |
- Lesson 0: Setup and the ASIC design flow
- Lesson 1: Introduction to Verilog
- Lesson 2: Synthesis
- Lesson 3: Place and route
- Lesson 4: Gate level simulation
- Lesson 5: Estimating timing and power
- Lesson 6: SoC design and interconnects
- Lesson 7: Design for test
- Synopsys Reference Design Methodology
- Synopsys VCS
- Synopsys DC
- Synopsys ICC
- Synopsys PrimeTime
- Plug Synopsys office hours
- Link to userguides
- Link to ece5745