This is an HDMI output example for MicroPhase A7-Lite FPGA board with an XC7A100T (Artix-7) FPGA.
When creating a Vivado project, please select xc7a100tfgg484-1 as an FPGA.
Using Clocking Wizard of Vivado, please create an IP that inputs a 50MHz clock signal and outputs 25MHz and 250MHz clock signals. Don't forget to disable all Optional Inputs/Outputs for MMCM/PLL!
The HDMI display shows the following pattern.
a7-lite_hdmi.mp4
This table shows the hardware utilization of post-implementation.
