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Nibble Mode fix
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kcelebi committed Apr 3, 2023
1 parent 69916d1 commit a1ccecb
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Showing 10 changed files with 33 additions and 7 deletions.
Binary file modified riscv_assembler/__pycache__/__init__.cpython-38.pyc
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Binary file modified riscv_assembler/__pycache__/convert.cpython-38.pyc
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30 changes: 26 additions & 4 deletions riscv_assembler/convert.py
Original file line number Diff line number Diff line change
Expand Up @@ -103,8 +103,8 @@ def hex_mode(self, x):
'''
def convert(self, input, file = None):
output = Parser(input)

assert len(output) > 0, "Provided input yielded nothing from parser. Check input."
output = self.mod(output) # apply nibble mode, hex mode

if self.__output_mode == 'a':
return output
Expand All @@ -119,22 +119,44 @@ def convert(self, input, file = None):
raise NotImplementedError()

def write_to_file(self, output, file):
if file[-4:] == '.bin':
extension = file[-4:]

if extension == '.bin':
with open(file, 'wb') as f:
for instr in output:
byte_array = [instr[i:i+8] for i in range(0,len(instr),8)]
byte_list = [int(b,2) for b in byte_array]
f.write(bytearray(byte_list))

return

elif file[-4:] == '.txt':
elif extension == '.txt':
with open(file, 'w') as f:
for instr in output:
f.write(instr + "\n")

return

elif extension == '.csv':
raise NotImplementedError()

elif extension == '.dat':
raise NotImplementedError()

raise NotImplementedError()

def mod(self, output):
if self.__nibble_mode:
output = AssemblyConverter.apply_nibble(output)
elif self.__hex_mode:
output = AssemblyConverter.apply_hex(output)
return output

@staticmethod
def apply_nibble(output):
return ['\t'.join([elem[i:i+4] for i in range(0, len(elem), 4)]) for elem in output]

@staticmethod
def apply_hex(output):
raise NotImplementedError()
return ...

4 changes: 4 additions & 0 deletions riscv_assembler/depr_convert.py
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Expand Up @@ -3,6 +3,10 @@
from pathlib import Path
import os

'''
DEPRECATED VERSION AS OF MARCH 30th
'''

__all__ = ['AssemblyConverter']
class WrongInstructionSize( Exception ):
#raised when instruction size is not 32 bits
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2 changes: 1 addition & 1 deletion setup.py
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@

setuptools.setup(
name="riscv-assembler",
version="1.0.16",
version="2.0.0",
author="Kaya Çelebi",
author_email="kayacelebi17@gmail.com",
description="RISC-V assembler",
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4 changes: 2 additions & 2 deletions tests/test_class.py
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Expand Up @@ -79,13 +79,13 @@ def test_1():
def test_2():
assert func2() == ["a", "f"], "Test 2 Failed"

'''def test_4():
def test_4():
assert func4() == ['0000\t0000\t0000\t0000\t0000\t0000\t1011\t0011'], "Test 4 Failed"

def test_5():
assert func5() == ['0000\t0010\t0000\t0100\t0000\t0010\t1001\t0011'], "Test 5 Failed"

def test_7():
'''def test_7():
assert func7() == 4
def test_8():
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