app/bench: fix optional USER_IDT_ENABLE=0

Also make sure the APIC interrupt vector is never accidentally restored
to 0x00.

app/bench/main.c

@@ -186,7 +186,7 @@ void attacker_config_page_table(void)
 int main( int argc, char **argv )
 {
 	sgx_launch_token_t token = {0};
-	int apic_fd, encl_strlen = 0, updated = 0;
+    int apic_fd, encl_strlen = 0, updated = 0, vec=0;
     idt_t idt = {0};
 
    	info_event("Creating enclave...");
@@ -204,8 +204,9 @@ int main( int argc, char **argv )
         //dump_idt(&idt);
         apic_timer_oneshot(IRQ_VECTOR);
     #else
-        info_event("Establishing user space APIC mapping (with kernel space handler)");
-        apic_timer_oneshot(LOCAL_TIMER_VECTOR);
+        vec = (apic_read(APIC_LVTT) & 0xff);
+        info_event("Establishing user space APIC mapping with kernel space handler (vector=%d)", vec);
+        apic_timer_oneshot(vec);
     #endif
 
     /* TODO for some reason the Dell Latitude machine first needs 2 SW IRQs

libsgxstep/apic.c

@@ -79,14 +79,17 @@ int apic_timer_oneshot(uint8_t vector)
 
 int apic_timer_deadline(void)
 {
-    apic_write(APIC_LVTT, apic_lvtt);
-    apic_write(APIC_TDCR, apic_tdcr);
-    libsgxstep_info("Restored APIC_LVTT=%x/TDCR=%x)",
-        apic_read(APIC_LVTT), apic_read(APIC_TDCR));
+    if (apic_lvtt)
+    {
+        apic_write(APIC_LVTT, apic_lvtt);
+        apic_write(APIC_TDCR, apic_tdcr);
+        libsgxstep_info("Restored APIC_LVTT=%x/TDCR=%x)",
+            apic_read(APIC_LVTT), apic_read(APIC_TDCR));
+        apic_lvtt = apic_tdcr = 0x0;
+    }
 
     /* writing a non-zero value to the TSC_DEADLINE MSR will arm the timer */
     #if APIC_CONFIG_MSR
         wrmsr_on_cpu(IA32_TSC_DEADLINE_MSR, get_cpu(), 1);
     #endif
-    apic_lvtt = apic_tdcr = 0x0;
 }