libsgxstep: Support APIC inter-processor interrupts

jovanbulck · Sep 2, 2023 · b933a08 · b933a08
1 parent e5598c1
commit b933a08
Show file tree

Hide file tree

Showing 5 changed files with 39 additions and 20 deletions.
diff --git a/libsgxstep/apic.c b/libsgxstep/apic.c
@@ -57,11 +57,18 @@ void apic_init(void)
     apic_base = remap(apic_base_addr);
     libsgxstep_info("established local memory mapping for APIC_BASE=%p at %p", (void*) apic_base_addr, apic_base);
 
-    libsgxstep_info("APIC_ID=%x; LVTT=%x; TDCR=%x", apic_read(APIC_ID),
+    libsgxstep_info("APIC_ID=%#x; LVTT=%#x; TDCR=%#x", apic_id(),
         apic_read(APIC_LVTT), apic_read(APIC_TDCR));
     ASSERT(apic_read(APIC_ID) != -1);
 }
 
+uint8_t apic_id(void)
+{
+    uint32_t id = apic_read(APIC_ID);
+    id = (id & APIC_ID_MASK) >> APIC_ID_SHIFT;
+    return (uint8_t) id;
+}
+
 int apic_timer_oneshot(uint8_t vector)
 {
     /* NOTE: APIC will be auto-restored when closing /dev/sgx-step */

diff --git a/libsgxstep/apic.h b/libsgxstep/apic.h
@@ -33,17 +33,22 @@
     #define APIC_BASE               0xfee00000
 #endif
 
-#define APIC_ICR                    0x300
+#define APIC_ICR_LOW                0x300
+#define APIC_ICR_HIGH               0x310
+
 #define APIC_LVTT                   0x320
 #define APIC_TDCR                   0x3e0
 #define APIC_TMICT                  0x380
 #define APIC_TMCCT                  0x390
 
 #define APIC_ID                     0x20
+#define APIC_ID_SHIFT               24
+#define APIC_ID_MASK                (0xff << APIC_ID_SHIFT)
+
 #define APIC_EOI                    0xb0
 
-#define APIC_TPR	                0x80
-#define APIC_PPR	                0xa0
+#define APIC_TPR	            0x80
+#define APIC_PPR	            0xa0
 
 #define APIC_TDR_DIV_1              0xb
 #define APIC_TDR_DIV_2              0x0
@@ -52,10 +57,13 @@
 
 #define APIC_IPI_CFG                0xc08f1
 
-#define APIC_ICR_VECTOR(n)      (n & 0xFF)
-#define APIC_ICR_DELIVERY_FIXED (0x0 << 8)
-#define APIC_ICR_LEVEL_ASSERT   (0x1 << 14)
-#define APIC_ICR_DEST_SELF      (0x1 << 18)
+#define APIC_ICR_VECTOR(n)          (n & 0xFF)
+#define APIC_ICR_DELIVERY_FIXED     (0x0 << 8)
+#define APIC_ICR_LEVEL_ASSERT       (0x1 << 14)
+#define APIC_ICR_DEST_SELF          (0x1 << 18)
+#define APIC_ICR_DEST_PHYSICAL      (0x0 << 11)
+#define APIC_ICR_DEST_LOGICAL       (0x1 << 11)
+#define APIC_ICR_DEST_MASK          0xff000000
 
 extern void* apic_base;
 extern uint32_t apic_lvtt;
@@ -85,10 +93,11 @@ static inline uint32_t apic_read(uint32_t reg)
     return *((volatile uint32_t *)(apic_base + reg));
 }
 
-//#define apic_send_ipi() apic_write(APIC_ICR, APIC_IPI_CFG)
+//#define apic_send_ipi() apic_write(APIC_ICR_LOW, APIC_IPI_CFG)
 #define apic_timer_irq(tsc) apic_write(APIC_TMICT, tsc);
-#define apic_send_ipi_self(n) apic_write(APIC_ICR, APIC_ICR_VECTOR(n) | APIC_ICR_DELIVERY_FIXED | APIC_ICR_LEVEL_ASSERT | APIC_ICR_DEST_SELF)
+#define apic_send_ipi_self(n) apic_write(APIC_ICR_LOW, APIC_ICR_VECTOR(n) | APIC_ICR_DELIVERY_FIXED | APIC_ICR_LEVEL_ASSERT | APIC_ICR_DEST_SELF)
 
+uint8_t apic_id(void);
 int apic_timer_oneshot(uint8_t vector);
 int apic_timer_deadline(uint8_t vector);
 void apic_timer_deadline_irq(int tsc_diff);

diff --git a/libsgxstep/config.h b/libsgxstep/config.h
@@ -38,7 +38,7 @@
 
 #define VICTIM_CPU                  1
 #define NUM_CORES                   4
-#define SPY_CPU                     (VICTIM_CPU + NUM_CORES)
+#define SPY_CPU                     (NUM_CORES-1)
 
 /*
  * XXX Configure APIC timer interval for next interrupt.

diff --git a/libsgxstep/idt.h b/libsgxstep/idt.h
@@ -43,5 +43,7 @@ void install_kernel_irq_handler(idt_t *idt, void *asm_handler, int vector);
 
 void __ss_irq_handler(void);
 extern int volatile __ss_irq_fired, __ss_irq_count, __ss_irq_cpl;
+extern uint64_t __ss_irq_rip;
+extern uint64_t nemesis_tsc_aex;
 
 #endif
diff --git a/libsgxstep/sched.c b/libsgxstep/sched.c
@@ -65,22 +65,23 @@ int get_core_id(int cpu_id)
     FILE *fd;
     ASSERT((fd = fopen("/proc/cpuinfo", "r")) >= 0);
 
-    int cur_cpu_id = -1, core_id = -1, core_id_prev = -1;
+    int cur_cpu_id = -1, core_id = -1;
     char buf[100];
     while (fgets(buf, sizeof(buf), fd))
     {
-        sscanf(buf, "core id : %d %*[^\n]", &core_id);
-        if (core_id != core_id_prev)
+        sscanf(buf, "processor : %d %*[^\n]", &cur_cpu_id);
+        if (sscanf(buf, "core id : %d %*[^\n]", &core_id) > 0)
         {
-            cur_cpu_id++;
-            if (cur_cpu_id == cpu_id) break;
+            if (cur_cpu_id == cpu_id)
+            {
+                debug("Found cpu_id=%d -> core_id=%d", cpu_id, core_id);
+                return core_id;
+            }
         }
-        core_id_prev = core_id;
     }
 
-    debug("Found cpu_id=%d -> core_id=%d", cpu_id, core_id);
-    ASSERT( cur_cpu_id == cpu_id );
-    return core_id;
+    ASSERT( 0 && "core id not found in /proc/cpuinfo");
+    return -1;
 }
 
 unsigned int pstate_max_perf_pct( void )