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* Issue#1402: Adding rule interface_incomplete_type_declaration_500 * Adding rule interface_incomplete_type_declaration_501. * Adding rule interface_incomplete_type_declaration_600. * Adding rule interface_incomplete_type_declaration_601. * Fixing style issues.
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Original file line number | Diff line number | Diff line change |
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.. include:: includes.rst | ||
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Interface Incomplete Type Declaration Rules | ||
------------------------------------------- | ||
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interface_incomplete_type_declaration_500 | ||
######################################### | ||
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|phase_6| |error| |case| |case_keyword| | ||
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This rule checks the **type** keyword has proper case. | ||
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|configuring_uppercase_and_lowercase_rules_link| | ||
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**Violation** | ||
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.. code-block:: vhdl | ||
generic ( | ||
TYPE generic_data_type | ||
**Fix** | ||
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.. code-block:: vhdl | ||
generic ( | ||
type generic_data_type | ||
interface_incomplete_type_declaration_501 | ||
######################################### | ||
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|phase_6| |error| |case| |case_name| | ||
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This rule checks the type name has proper case. | ||
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|configuring_uppercase_and_lowercase_rules_link| | ||
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**Violation** | ||
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.. code-block:: vhdl | ||
generic ( | ||
type GENERIC_DATA_TYPE | ||
**Fix** | ||
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.. code-block:: vhdl | ||
generic ( | ||
type generic_data_type | ||
interface_incomplete_type_declaration_600 | ||
######################################### | ||
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|phase_7| |disabled| |error| |unfixable| |naming| | ||
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This rule checks for valid prefixes of type names. | ||
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.. NOTE:: The default prefix is *gt_*. | ||
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|configuring_prefix_and_suffix_rules_link| | ||
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**Violation** | ||
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.. code-block:: vhdl | ||
generic ( | ||
type generic_data_type | ||
**Fix** | ||
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.. code-block:: vhdl | ||
generic ( | ||
type gt_generic_data_type | ||
interface_incomplete_type_declaration_601 | ||
######################################### | ||
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|phase_7| |disabled| |error| |unfixable| |naming| | ||
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This rule checks for valid suffixes of type names. | ||
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.. NOTE:: The default prefix is *_gt*. | ||
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|configuring_prefix_and_suffix_rules_link| | ||
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**Violation** | ||
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.. code-block:: vhdl | ||
generic ( | ||
type generic_data_type | ||
**Fix** | ||
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.. code-block:: vhdl | ||
generic ( | ||
type generic_data_type_gt |
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36 changes: 36 additions & 0 deletions
36
tests/interface_incomplete_type_declaration/rule_500_test_input.fixed_lower.vhd
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Original file line number | Diff line number | Diff line change |
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entity fifo is | ||
generic ( | ||
type generic_data_type; | ||
type generic_data_type; | ||
type generic_data_type | ||
); | ||
port ( | ||
data_in : generic_data_type | ||
); | ||
end entity fifo; | ||
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architecture rtl of fifo is | ||
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component buffer is | ||
generic ( | ||
type generic_data_type; | ||
type generic_data_type; | ||
type generic_data_type | ||
); | ||
port ( | ||
data_in : generic_data_type | ||
); | ||
end component buffer; | ||
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begin | ||
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buf1 : buffer | ||
generic map ( | ||
generic_data_type => std_logic | ||
) | ||
port map ( | ||
data_in => '0' | ||
); | ||
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end architecture rtl; |
36 changes: 36 additions & 0 deletions
36
tests/interface_incomplete_type_declaration/rule_500_test_input.fixed_upper.vhd
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Original file line number | Diff line number | Diff line change |
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|
||
entity fifo is | ||
generic ( | ||
TYPE generic_data_type; | ||
TYPE generic_data_type; | ||
TYPE generic_data_type | ||
); | ||
port ( | ||
data_in : generic_data_type | ||
); | ||
end entity fifo; | ||
|
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architecture rtl of fifo is | ||
|
||
component buffer is | ||
generic ( | ||
TYPE generic_data_type; | ||
TYPE generic_data_type; | ||
TYPE generic_data_type | ||
); | ||
port ( | ||
data_in : generic_data_type | ||
); | ||
end component buffer; | ||
|
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begin | ||
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buf1 : buffer | ||
generic map ( | ||
generic_data_type => std_logic | ||
) | ||
port map ( | ||
data_in => '0' | ||
); | ||
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||
end architecture rtl; |
36 changes: 36 additions & 0 deletions
36
tests/interface_incomplete_type_declaration/rule_500_test_input.vhd
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,36 @@ | ||
|
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entity fifo is | ||
generic ( | ||
type generic_data_type; | ||
TyPe generic_data_type; | ||
TYPE generic_data_type | ||
); | ||
port ( | ||
data_in : generic_data_type | ||
); | ||
end entity fifo; | ||
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architecture rtl of fifo is | ||
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||
component buffer is | ||
generic ( | ||
type generic_data_type; | ||
TyPe generic_data_type; | ||
TYPE generic_data_type | ||
); | ||
port ( | ||
data_in : generic_data_type | ||
); | ||
end component buffer; | ||
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begin | ||
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buf1 : buffer | ||
generic map ( | ||
generic_data_type => std_logic | ||
) | ||
port map ( | ||
data_in => '0' | ||
); | ||
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||
end architecture rtl; |
36 changes: 36 additions & 0 deletions
36
tests/interface_incomplete_type_declaration/rule_501_test_input.fixed_lower.vhd
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,36 @@ | ||
|
||
entity fifo is | ||
generic ( | ||
type generic_data_type; | ||
type generic_data_type; | ||
type generic_data_type | ||
); | ||
port ( | ||
data_in : generic_data_type | ||
); | ||
end entity fifo; | ||
|
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architecture rtl of fifo is | ||
|
||
component buffer is | ||
generic ( | ||
type generic_data_type; | ||
type generic_data_type; | ||
type generic_data_type | ||
); | ||
port ( | ||
data_in : generic_data_type | ||
); | ||
end component buffer; | ||
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begin | ||
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buf1 : buffer | ||
generic map ( | ||
generic_data_type => std_logic | ||
) | ||
port map ( | ||
data_in => '0' | ||
); | ||
|
||
end architecture rtl; |
36 changes: 36 additions & 0 deletions
36
tests/interface_incomplete_type_declaration/rule_501_test_input.fixed_upper.vhd
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,36 @@ | ||
|
||
entity fifo is | ||
generic ( | ||
type GENERIC_DATA_TYPE; | ||
type GENERIC_DATA_TYPE; | ||
type GENERIC_DATA_TYPE | ||
); | ||
port ( | ||
data_in : generic_data_type | ||
); | ||
end entity fifo; | ||
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architecture rtl of fifo is | ||
|
||
component buffer is | ||
generic ( | ||
type GENERIC_DATA_TYPE; | ||
type GENERIC_DATA_TYPE; | ||
type GENERIC_DATA_TYPE | ||
); | ||
port ( | ||
data_in : generic_data_type | ||
); | ||
end component buffer; | ||
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begin | ||
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buf1 : buffer | ||
generic map ( | ||
generic_data_type => std_logic | ||
) | ||
port map ( | ||
data_in => '0' | ||
); | ||
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end architecture rtl; |
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