diff --git a/applications/sdp/mspi/CMakeLists.txt b/applications/sdp/mspi/CMakeLists.txt index 338d1d7ad562..d74d1381a5e3 100644 --- a/applications/sdp/mspi/CMakeLists.txt +++ b/applications/sdp/mspi/CMakeLists.txt @@ -9,11 +9,11 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) project(sdp_mspi) -sdp_assembly_generate("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c") -sdp_assembly_check("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c") -sdp_assembly_prepare_install("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c") +# sdp_assembly_generate("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c") +# sdp_assembly_check("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c") +# sdp_assembly_prepare_install("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c") target_sources(app PRIVATE src/main.c) -target_sources(app PRIVATE src/hrt/hrt.s) +target_sources(app PRIVATE src/hrt/hrt.c) -add_dependencies(app asm_check) +# add_dependencies(app asm_check) diff --git a/applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.conf b/applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.conf index 4a8a0c4d05c6..3a8b91d83e57 100644 --- a/applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.conf +++ b/applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.conf @@ -7,9 +7,9 @@ CONFIG_LOG=n CONFIG_I2C=n CONFIG_WATCHDOG=n CONFIG_GPIO=n -CONFIG_PINCTRL=n +CONFIG_PINCTRL=y CONFIG_SPI=n -CONFIG_SERIAL=n +CONFIG_SERIAL=y CONFIG_FLASH=n # Power management @@ -18,7 +18,7 @@ CONFIG_PM=n # Interrupts CONFIG_DYNAMIC_INTERRUPTS=n CONFIG_IRQ_OFFLOAD=n -CONFIG_GEN_SW_ISR_TABLE=n +CONFIG_GEN_SW_ISR_TABLE=y # Memory protection CONFIG_THREAD_STACK_INFO=n @@ -26,15 +26,15 @@ CONFIG_THREAD_CUSTOM_DATA=n CONFIG_FPU=n # Boot -CONFIG_BOOT_BANNER=n +CONFIG_BOOT_BANNER=y CONFIG_NCS_BOOT_BANNER=n # Console -CONFIG_CONSOLE=n -CONFIG_UART_CONSOLE=n -CONFIG_STDOUT_CONSOLE=n -CONFIG_PRINTK=n -CONFIG_EARLY_CONSOLE=n +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_STDOUT_CONSOLE=y +CONFIG_PRINTK=y +CONFIG_EARLY_CONSOLE=y # Build CONFIG_SIZE_OPTIMIZATIONS=y @@ -45,4 +45,5 @@ CONFIG_SYS_CLOCK_EXISTS=n CONFIG_OUTPUT_DISASSEMBLY=y CONFIG_COMMON_LIBC_MALLOC=n -CONFIG_COMPILER_OPT="-fshort-enums" \ No newline at end of file +# additional compiler flags +CONFIG_COMPILER_OPT="-fshort-enums" diff --git a/applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay b/applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay index c3c8081a6be0..2602dafa878f 100644 --- a/applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay +++ b/applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay @@ -10,12 +10,12 @@ #address-cells = <1>; #size-cells = <1>; - sram_tx: memory@2003c000 { - reg = <0x2003c000 0x0800>; + sram_tx: memory@2003a000 { + reg = <0x2003a000 0x0800>; }; - sram_rx: memory@2003c800 { - reg = <0x2003c800 0x0800>; + sram_rx: memory@2003a800 { + reg = <0x2003a800 0x0800>; }; }; }; @@ -33,16 +33,16 @@ }; &cpuflpr_rram { - reg = <0x17a000 DT_SIZE_K(12)>; + reg = <0x178000 DT_SIZE_K(20)>; }; &cpuflpr_code_partition { - reg = <0x0 DT_SIZE_K(12)>; + reg = <0x0 DT_SIZE_K(20)>; }; &cpuflpr_sram { - reg = <0x2003d000 DT_SIZE_K(12)>; - ranges = <0x0 0x2003d000 0x3000>; + reg = <0x2003b000 DT_SIZE_K(20)>; + ranges = <0x0 0x2003b000 0x5000>; }; &cpuflpr_vevif_rx { @@ -85,7 +85,7 @@ }; &uart30 { - status = "disabled"; + status = "okay"; }; &pwm20 { diff --git a/applications/sdp/mspi/src/hrt/hrt.c b/applications/sdp/mspi/src/hrt/hrt.c index 04f91eecfa0b..5efe8c6b86f5 100644 --- a/applications/sdp/mspi/src/hrt/hrt.c +++ b/applications/sdp/mspi/src/hrt/hrt.c @@ -8,6 +8,7 @@ #include #include #include +#include void hrt_write(volatile struct hrt_ll_xfer xfer_ll_params) { @@ -100,7 +101,6 @@ void hrt_write(volatile struct hrt_ll_xfer xfer_ll_params) /* Disable CS */ if (!xfer_ll_params.ce_hold) { - out = nrf_vpr_csr_vio_out_get(); if (xfer_ll_params.ce_polarity == MSPI_CE_ACTIVE_LOW) { @@ -114,3 +114,123 @@ void hrt_write(volatile struct hrt_ll_xfer xfer_ll_params) /* Stop counter */ nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_STOP); } + +void hrt_read(volatile struct hrt_ll_xfer xfer_ll_params) +{ + uint16_t out; + uint32_t word_ctr = 0; + + NRFX_ASSERT((xfer_ll_params.last_word_clocks != 1) || (xfer_ll_params.words == 1)) + + /* Enable CS */ + out = nrf_vpr_csr_vio_out_get(); + + if (xfer_ll_params.ce_polarity == MSPI_CE_ACTIVE_LOW) { + out = BIT_SET_VALUE(out, xfer_ll_params.ce_vio, VPRCSR_NORDIC_OUT_LOW); + } else { + out = BIT_SET_VALUE(out, xfer_ll_params.ce_vio, VPRCSR_NORDIC_OUT_HIGH); + } + nrf_vpr_csr_vio_out_set(out); + + switch (xfer_ll_params.bit_order) { + case HRT_BO_NORMAL: + nrf_vpr_csr_vio_out_buffered_set(((uint32_t *)xfer_ll_params.data)[word_ctr++]); + break; + case HRT_BO_REVERSED_BYTE: + nrf_vpr_csr_vio_out_buffered_reversed_byte_set( + ((uint32_t *)xfer_ll_params.data)[word_ctr++]); + break; + case HRT_BO_REVERSED_WORD: + nrf_vpr_csr_vio_out_buffered_reversed_word_set( + ((uint32_t *)xfer_ll_params.data)[word_ctr++]); + break; + } + + /* Counter settings */ + nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_RELOAD); + nrf_vpr_csr_vtim_count_mode_set(1, NRF_VPR_CSR_VTIM_COUNT_RELOAD); + + /* TODO: Jira ticket: NRFX-6703 + * Top value of VTIM. This will determine clock frequency + * (SPI_CLOCK ~= CPU_CLOCK / (2 * TOP)). + * Calculate this value based on frequency + */ + nrf_vpr_csr_vtim_simple_counter_top_set(0, 32); + /* Trigger data capture every two clock cycles */ + nrf_vpr_csr_vtim_simple_counter_top_set(1, 2 * (32 + 1) - 1); + + /* Start both counters */ + nrf_vpr_csr_vtim_combined_counter_set( + (32 << VPRCSR_NORDIC_CNT_CNT0_Pos) + + (32 << VPRCSR_NORDIC_CNT_CNT1_Pos)); + + nrf_vpr_csr_vtim_simple_wait_set(0, false, 0); + + while (word_ctr < xfer_ll_params.words) { + + switch (xfer_ll_params.bit_order) { + case HRT_BO_NORMAL: + nrf_vpr_csr_vio_out_buffered_set( + ((uint32_t *)xfer_ll_params.data)[word_ctr]); + ((uint32_t *)xfer_ll_params.rx_data)[word_ctr] = + nrf_vpr_csr_vio_in_buffered_get(); + break; + case HRT_BO_REVERSED_BYTE: + nrf_vpr_csr_vio_out_buffered_reversed_byte_set( + ((uint32_t *)xfer_ll_params.data)[word_ctr]); + ((uint32_t *)xfer_ll_params.rx_data)[word_ctr] = + nrf_vpr_csr_vio_in_buffered_reversed_byte_get(); + break; + case HRT_BO_REVERSED_WORD: + nrf_vpr_csr_vio_out_buffered_reversed_word_set( + ((uint32_t *)xfer_ll_params.data)[word_ctr]); + ((uint32_t *)xfer_ll_params.rx_data)[word_ctr] = + nrf_vpr_csr_vio_in_buffered_get(); + break; + } + word_ctr++; + } + + nrf_vpr_csr_vio_shift_cnt_out_buffered_set(0); + while (nrf_vpr_csr_vio_shift_cnt_out_get() > 0) {}; + + if (xfer_ll_params.eliminate_last_pulse) { + nrf_vpr_csr_vtim_simple_wait_set(0, false, 0); + } + + nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_STOP); + nrf_vpr_csr_vtim_simple_wait_set(0, false, 0); + + switch (xfer_ll_params.bit_order) { + case HRT_BO_NORMAL: + ((uint32_t *)xfer_ll_params.rx_data)[word_ctr] = nrf_vpr_csr_vio_in_buffered_get(); + break; + case HRT_BO_REVERSED_BYTE: + ((uint32_t *)xfer_ll_params.rx_data)[word_ctr] = + nrf_vpr_csr_vio_in_buffered_reversed_byte_get(); + break; + case HRT_BO_REVERSED_WORD: + ((uint32_t *)xfer_ll_params.rx_data)[word_ctr] = nrf_vpr_csr_vio_in_buffered_get(); + break; + } + + nrf_vpr_csr_vio_shift_cnt_out_set(0); + nrf_vpr_csr_vio_mode_out_t out_mode = {0}; + nrf_vpr_csr_vio_mode_out_set(&out_mode); + nrf_vpr_csr_vio_mode_in_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS); + + /* Disable CS */ + if (xfer_ll_params.ce_hold == false) { + out = nrf_vpr_csr_vio_out_get(); + + if (xfer_ll_params.ce_polarity == MSPI_CE_ACTIVE_LOW) { + out = BIT_SET_VALUE(out, xfer_ll_params.ce_vio, VPRCSR_NORDIC_OUT_HIGH); + } else { + out = BIT_SET_VALUE(out, xfer_ll_params.ce_vio, VPRCSR_NORDIC_OUT_LOW); + } + nrf_vpr_csr_vio_out_set(out); + } + + /* Stop counters */ + nrf_vpr_csr_vtim_count_mode_set(1, NRF_VPR_CSR_VTIM_COUNT_STOP); +} diff --git a/applications/sdp/mspi/src/hrt/hrt.h b/applications/sdp/mspi/src/hrt/hrt.h index 5d9624375925..a18725a6f02d 100644 --- a/applications/sdp/mspi/src/hrt/hrt.h +++ b/applications/sdp/mspi/src/hrt/hrt.h @@ -39,6 +39,7 @@ struct hrt_ll_xfer { /** @brief Buffer for RX/TX data */ uint8_t *data; + uint8_t *rx_data; /** @brief CEIL(buffer_length_bits/32) */ @@ -75,7 +76,7 @@ struct hrt_ll_xfer { uint8_t ce_vio; /** @brief If true chip enable pin will be left active after transfer */ - uint8_t ce_hold; + bool ce_hold; /** @brief Chip enable pin polarity in enabled state. */ enum mspi_ce_polarity ce_polarity; @@ -88,10 +89,18 @@ struct hrt_ll_xfer { /** @brief Write. * - * Function to be used to write data on SPI. + * Function to be used to write data on MSPI. * * @param[in] xfer_ll_params Low level transfer parameters. */ void hrt_write(volatile struct hrt_ll_xfer xfer_ll_params); +/** @brief Read. + * + * Function to be used to read data from MSPI. + * + * @param[in] xfer_ll_params Low level transfer parameters. + */ +void hrt_read(volatile struct hrt_ll_xfer xfer_ll_params); + #endif /* _HRT_H__ */ diff --git a/applications/sdp/mspi/src/hrt/hrt.s b/applications/sdp/mspi/src/hrt/hrt.s index 75cc1f3dbe51..1691d44fc9e2 100644 --- a/applications/sdp/mspi/src/hrt/hrt.s +++ b/applications/sdp/mspi/src/hrt/hrt.s @@ -143,6 +143,7 @@ hrt_write: csrw 3016, a3 #NO_APP j .L11 +<<<<<<< HEAD .L9: lw a3,16(a0) .L28: @@ -182,3 +183,149 @@ hrt_write: and a5,a5,a3 j .L30 .size hrt_write, .-hrt_write +======= + .size write_quad_by_word, .-write_quad_by_word + .section .text.read_single_by_word,"ax",@progbits + .align 1 + .globl read_single_by_word + .type read_single_by_word, @function +read_single_by_word: + lbu a5,0(a0) + addi sp,sp,-4 + slli a5,a5,1 + addi a5,a5,1 + sw a5,0(sp) + #APP + csrr a5, 3009 + #NO_APP + slli a5,a5,16 + srli a5,a5,16 + ori a4,a5,2 + #APP + csrw 3009, a4 + #NO_APP + andi a5,a5,-5 + #APP + csrw 3009, a5 + csrr a4, 3008 + #NO_APP + li a5,65536 + addi a3,a5,-1 + and a4,a4,a3 + #APP + csrw 3008, a4 + #NO_APP + addi a5,a5,4 + #APP + csrw 3043, a5 + csrw 3045, 2 + csrr a5, 1996 + #NO_APP + andi a5,a5,17 + ori a5,a5,256 + #APP + csrw 1996, a5 + csrw 2000, 2 + csrw 2001, 2 + #NO_APP + lbu a5,0(a0) + andi a5,a5,0xff + #APP + csrr a4, 2003 + #NO_APP + li a2,-65536 + and a4,a4,a2 + or a5,a5,a4 + #APP + csrw 2003, a5 + #NO_APP + lw a5,0(sp) + #APP + csrr a4, 2003 + #NO_APP + addi a5,a5,-1 + and a4,a4,a3 + slli a5,a5,16 + or a5,a5,a4 + #APP + csrw 2003, a5 + #NO_APP + lbu a5,1(a0) + #APP + csrw 3021, a5 + csrr a5, 3008 + #NO_APP + lbu a3,10(a0) + slli a5,a5,16 + srli a5,a5,16 + ori a4,a5,32 + beq a3,zero,.L19 + andi a5,a5,-33 + slli a4,a5,16 + srli a4,a4,16 +.L19: + #APP + csrw 3008, a4 + #NO_APP + lbu a4,0(a0) + lw a5,0(sp) + slli a5,a5,16 + add a5,a5,a4 + #APP + csrw 2002, a5 + #NO_APP + li a2,65536 + li a5,0 + addi a2,a2,-1 +.L20: + lbu a4,8(a0) + bgtu a4,a5,.L21 + li a5,65536 + #APP + csrw 3043, a5 + csrw 3045, 0 + #NO_APP + lbu a5,9(a0) + bne a5,zero,.L22 + #APP + csrr a5, 3008 + #NO_APP + lbu a3,10(a0) + slli a5,a5,16 + srli a5,a5,16 + ori a4,a5,32 + beq a3,zero,.L24 + andi a5,a5,-33 + slli a4,a5,16 + srli a4,a4,16 +.L24: + andi a4,a4,-2 + #APP + csrw 3008, a4 + #NO_APP +.L22: + #APP + csrw 2000, 0 + csrw 2001, 0 + #NO_APP + addi sp,sp,4 + jr ra +.L21: + #APP + csrr a4, 3021 + #NO_APP + andi a4,a4,1 + beq a4,zero,.L21 + #APP + csrr a3, 3018 + #NO_APP + lw a4,4(a0) + slli a1,a5,2 + and a3,a3,a2 + add a4,a4,a1 + addi a5,a5,1 + sw a3,0(a4) + andi a5,a5,0xff + j .L20 + .size read_single_by_word, .-read_single_by_word +>>>>>>> 784011ca31 (applications: sdp: mspi: Add RX path to SDP MSPI) diff --git a/applications/sdp/mspi/src/main.c b/applications/sdp/mspi/src/main.c index 1dc57652f9a6..7b59b7277d9f 100644 --- a/applications/sdp/mspi/src/main.c +++ b/applications/sdp/mspi/src/main.c @@ -18,6 +18,8 @@ #include #include +#include +#include /************************************************* * DEFINES @@ -26,6 +28,7 @@ #define DATA_PINS_MAX 8 #define HRT_IRQ_PRIORITY 2 +#define HRT_VEVIF_IDX_READ 17 #define HRT_VEVIF_IDX_WRITE 18 #define PINCTL_PIN_NUM_MASK 0x0fU @@ -88,6 +91,7 @@ static const uint8_t pin_to_vio_map[] = { 10, /* Physical pin 10 */ }; +static volatile uint8_t clk_vio; static volatile uint8_t ce_vios_count; static volatile uint8_t ce_vios[CE_PINS_MAX]; static volatile uint8_t data_vios_count; @@ -98,35 +102,21 @@ static volatile struct mspi_xfer nrfe_mspi_xfer; static volatile struct mspi_xfer_packet nrfe_mspi_xfer_packet; static volatile struct hrt_ll_xfer xfer_ll_params; +static volatile uint8_t rx_buffer[512]; + static struct ipc_ept ep; static atomic_t ipc_atomic_sem = ATOMIC_INIT(0); -/************************************************* - * GLOBAL FUNCTION PROTOTYPES - *************************************************/ - -__attribute__((interrupt)) void hrt_handler_write(void); - -int main(void); - /************************************************* * LOCAL FUNCTION PROTOTYPES *************************************************/ - -static struct xfer_io_mode_cfg get_io_modes(enum mspi_io_mode mode); - -static void ep_bound(void *priv); - -static void ep_recv(const void *data, size_t len, void *priv); - -static void ll_prepare_transfer(enum base_io_mode xfer_mode, uint32_t data_length); - -static void configure_clock(enum mspi_cpp_mode cpp_mode); - -static void prepare_and_send_data(); - -static void process_packet(const void *data, size_t len); - +static void ll_prepare_transfer(uint16_t frame_width, enum mspi_xfer_direction xfer_dir, + uint32_t data_length); +static void ll_prepare_receive(uint16_t frame_width, enum mspi_xfer_direction dir, + uint32_t data_length); +static void dev_pins_configure(enum mspi_cpp_mode cpp_mode); +static void prepare_and_send_data(uint8_t *buffer, uint32_t data_length); +static void prepare_and_read_data(uint8_t *read_data, uint32_t data_length); static int backend_init(void); /************************************************* @@ -138,6 +128,11 @@ __attribute__((interrupt)) void hrt_handler_write(void) hrt_write(xfer_ll_params); } +__attribute__((interrupt)) void hrt_handler_read(void) +{ + hrt_read(xfer_ll_params); +} + int main(void) { int ret = backend_init(); @@ -146,6 +141,9 @@ int main(void) return 0; } + IRQ_DIRECT_CONNECT(HRT_VEVIF_IDX_READ, HRT_IRQ_PRIORITY, hrt_handler_read, 0); + nrf_vpr_clic_int_enable_set(NRF_VPRCLIC, VEVIF_IRQN(HRT_VEVIF_IDX_READ), true); + IRQ_DIRECT_CONNECT(HRT_VEVIF_IDX_WRITE, HRT_IRQ_PRIORITY, hrt_handler_write, 0); nrf_vpr_clic_int_enable_set(NRF_VPRCLIC, VEVIF_IRQN(HRT_VEVIF_IDX_WRITE), true); @@ -234,65 +232,23 @@ static void ep_bound(void *priv) atomic_set_bit(&ipc_atomic_sem, NRFE_MSPI_EP_BOUNDED); } -static void ep_recv(const void *data, size_t len, void *priv) +static void ll_prepare_transfer(uint16_t frame_width, enum mspi_xfer_direction xfer_dir, + uint32_t data_length) { - (void)priv; - - process_packet(data, len); -} - -static void ll_prepare_transfer(enum base_io_mode xfer_mode, uint32_t data_length) -{ - uint16_t dir; - uint16_t out; nrf_vpr_csr_vio_config_t config; nrf_vpr_csr_vio_mode_out_t out_mode = { .mode = NRF_VPR_CSR_VIO_SHIFT_OUTB_TOGGLE, - .frame_width = 1, + .frame_width = frame_width, }; - dir = nrf_vpr_csr_vio_dir_get(); - out = nrf_vpr_csr_vio_out_get(); - - switch (xfer_mode) { - case BASE_IO_MODE_SINGLE: - out_mode.frame_width = 1; - break; - case BASE_IO_MODE_DUAL: - out_mode.frame_width = 2; - break; - case BASE_IO_MODE_QUAD: - out_mode.frame_width = 4; - break; - case BASE_IO_MODE_OCTAL: - out_mode.frame_width = 8; - break; - } - - NRFX_ASSERT(data_vios_count >= out_mode.frame_width); - NRFX_ASSERT(data_length % out_mode.frame_width == 0) - - uint16_t direction = (nrfe_mspi_xfer_packet.dir == MSPI_TX) ? VPRCSR_NORDIC_DIR_OUTPUT - : VPRCSR_NORDIC_DIR_INPUT; - - for (uint8_t i = 0; i < out_mode.frame_width; i++) { - dir = BIT_SET_VALUE(dir, data_vios[i], direction); - out = BIT_SET_VALUE(out, data_vios[i], VPRCSR_NORDIC_OUT_LOW); - } + nrf_vpr_csr_vio_mode_out_set(&out_mode); - dir = BIT_SET_VALUE(dir, xfer_ll_params.ce_vio, VPRCSR_NORDIC_DIR_OUTPUT); - if (nrfe_mspi_dev_cfg.ce_polarity == MSPI_CE_ACTIVE_LOW) { - out = BIT_SET_VALUE(out, xfer_ll_params.ce_vio, VPRCSR_NORDIC_OUT_HIGH); - } else { - out = BIT_SET_VALUE(out, xfer_ll_params.ce_vio, VPRCSR_NORDIC_OUT_LOW); - } - nrf_vpr_csr_vio_dir_set(dir); - nrf_vpr_csr_vio_out_set(out); - nrf_vpr_csr_vio_mode_out_set(&out_mode); + ////////////////////////// nrf_vpr_csr_vio_mode_in_buffered_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS); + ////////////////////////// nrf_vpr_csr_vio_config_get(&config); config.input_sel = false; @@ -305,7 +261,7 @@ static void ll_prepare_transfer(enum base_io_mode xfer_mode, uint32_t data_lengt * (SPI_CLOCK ~= CPU_CLOCK / (2 * TOP)). * Calculate this value based on frequency */ - nrf_vpr_csr_vtim_simple_counter_top_set(0, 4); + nrf_vpr_csr_vtim_simple_counter_top_set(0, 32); /* Set number of shifts before OUTB needs to be updated. * First shift needs to be increased by 1. @@ -349,7 +305,65 @@ static void ll_prepare_transfer(enum base_io_mode xfer_mode, uint32_t data_lengt } } -static void configure_clock(enum mspi_cpp_mode cpp_mode) +static void ll_prepare_receive(uint16_t frame_width, enum mspi_xfer_direction xfer_dir, + uint32_t data_length) +{ + nrf_vpr_csr_vio_config_t config; + nrf_vpr_csr_vio_mode_out_t out_mode = { + .mode = NRF_VPR_CSR_VIO_SHIFT_OUTB_TOGGLE, + .frame_width = frame_width, + }; + + nrf_vpr_csr_vio_config_get(&config); + config.input_sel = true; + nrf_vpr_csr_vio_config_set(&config); + + nrf_vpr_csr_vio_mode_out_set(&out_mode); + + uint8_t last_word_length = data_length % BITS_IN_WORD; + uint8_t penultimate_word_length = BITS_IN_WORD; + + xfer_ll_params.words = NRFX_CEIL_DIV(data_length, BITS_IN_WORD); + xfer_ll_params.last_word = ((uint32_t *)xfer_ll_params.data)[xfer_ll_params.words - 1]; + + /* Due to hardware limitations it is not possible to send only 1 clock cycle. + * Therefore when data_length%32==1 last word is sent shorter (24bits) + * and the remaining byte and 1 bit is sent together. + */ + if (last_word_length == 0) { + + last_word_length = BITS_IN_WORD; + xfer_ll_params.last_word = + ((uint32_t *)xfer_ll_params.data)[xfer_ll_params.words - 1]; + + } else if ((last_word_length / out_mode.frame_width == 1) && (xfer_ll_params.words > 1)) { + + penultimate_word_length -= BITS_IN_BYTE; + last_word_length += BITS_IN_BYTE; + xfer_ll_params.last_word = + ((uint32_t *)xfer_ll_params.data)[xfer_ll_params.words - 2] >> + (BITS_IN_WORD - BITS_IN_BYTE) | + ((uint32_t *)xfer_ll_params.data)[xfer_ll_params.words - 1] << BITS_IN_BYTE; + } + + xfer_ll_params.last_word_clocks = last_word_length / out_mode.frame_width; + xfer_ll_params.penultimate_word_clocks = penultimate_word_length / out_mode.frame_width; + + if (xfer_ll_params.words == 1) { + nrf_vpr_csr_vio_shift_cnt_out_set(xfer_ll_params.last_word_clocks); + nrf_vpr_csr_vio_shift_cnt_out_buffered_set(xfer_ll_params.last_word_clocks - 1); + } else if (xfer_ll_params.words == 2) { + nrf_vpr_csr_vio_shift_cnt_out_set(xfer_ll_params.penultimate_word_clocks); + nrf_vpr_csr_vio_shift_cnt_out_buffered_set(xfer_ll_params.penultimate_word_clocks - 1); + } else { + nrf_vpr_csr_vio_shift_cnt_out_set(BITS_IN_WORD / out_mode.frame_width); + nrf_vpr_csr_vio_shift_cnt_out_buffered_set((BITS_IN_WORD / out_mode.frame_width) - 1); + } + + nrf_vpr_csr_vio_mode_in_buffered_set(NRF_VPR_CSR_VIO_MODE_IN_SHIFT); +} + +static void dev_pins_configure(enum mspi_cpp_mode cpp_mode) { nrf_vpr_csr_vio_config_t vio_config = { .input_sel = 0, @@ -360,89 +374,223 @@ static void configure_clock(enum mspi_cpp_mode cpp_mode) switch (cpp_mode) { case MSPI_CPP_MODE_0: { vio_config.clk_polarity = 0; - out = BIT_SET_VALUE(out, pin_to_vio_map[NRFE_MSPI_SCK_PIN_NUMBER], - VPRCSR_NORDIC_OUT_LOW); + out = BIT_SET_VALUE(out, clk_vio, VPRCSR_NORDIC_OUT_LOW); xfer_ll_params.eliminate_last_pulse = false; break; } case MSPI_CPP_MODE_1: { vio_config.clk_polarity = 1; - out = BIT_SET_VALUE(out, pin_to_vio_map[NRFE_MSPI_SCK_PIN_NUMBER], - VPRCSR_NORDIC_OUT_LOW); + out = BIT_SET_VALUE(out, clk_vio, VPRCSR_NORDIC_OUT_LOW); xfer_ll_params.eliminate_last_pulse = true; break; } case MSPI_CPP_MODE_2: { vio_config.clk_polarity = 1; - out = BIT_SET_VALUE(out, pin_to_vio_map[NRFE_MSPI_SCK_PIN_NUMBER], - VPRCSR_NORDIC_OUT_HIGH); + out = BIT_SET_VALUE(out, clk_vio, VPRCSR_NORDIC_OUT_HIGH); xfer_ll_params.eliminate_last_pulse = false; break; } case MSPI_CPP_MODE_3: { vio_config.clk_polarity = 0; - out = BIT_SET_VALUE(out, pin_to_vio_map[NRFE_MSPI_SCK_PIN_NUMBER], - VPRCSR_NORDIC_OUT_HIGH); + out = BIT_SET_VALUE(out, clk_vio, VPRCSR_NORDIC_OUT_HIGH); xfer_ll_params.eliminate_last_pulse = true; break; } } + + for (uint8_t i = 0; i < ce_vios_count; i++) { + if (nrfe_mspi_dev_cfg.ce_polarity == MSPI_CE_ACTIVE_LOW) { + out = BIT_SET_VALUE(out, ce_vios[i], VPRCSR_NORDIC_OUT_HIGH); + } else { + out = BIT_SET_VALUE(out, ce_vios[i], VPRCSR_NORDIC_OUT_LOW); + } + } + nrf_vpr_csr_vio_out_set(out); nrf_vpr_csr_vio_config_set(&vio_config); } -static void prepare_and_send_data() +static uint16_t set_frame_width_and_pins(enum base_io_mode io_mode, enum mspi_xfer_direction xfer_dir) +{ + uint16_t dir = VPRCSR_NORDIC_DIR_INPUT; + uint16_t frame_width = 0; + + switch (io_mode) { + case BASE_IO_MODE_SINGLE: + frame_width = 1; + break; + case BASE_IO_MODE_DUAL: + frame_width = 2; + break; + case BASE_IO_MODE_QUAD: + frame_width = 4; + break; + case BASE_IO_MODE_OCTAL: + frame_width = 8; + break; + } + + NRFX_ASSERT(data_vios_count >= frame_width); + NRFX_ASSERT(data_length % frame_width == 0) + + dir = nrf_vpr_csr_vio_dir_get(); + for (uint8_t i = 0; i < frame_width; i++) { + dir = BIT_SET_VALUE(dir, data_vios[i], VPRCSR_NORDIC_DIR_OUTPUT); //(xfer_dir == MSPI_TX) + //? VPRCSR_NORDIC_DIR_OUTPUT + //: VPRCSR_NORDIC_DIR_INPUT); + } + nrf_vpr_csr_vio_dir_set(dir); + + return frame_width; +} + +static void prepare_and_send_data(uint8_t *buffer, uint32_t data_length) { NRFX_ASSERT(nrfe_mspi_dev_cfg.ce_num < ce_vios_count); struct xfer_io_mode_cfg xfer_modes = get_io_modes(nrfe_mspi_dev_cfg.io_mode); uint32_t data; - - /* Send command */ + uint16_t frame_width; /* TODO: Jira ticket: NRFX-6703 * Device waits this time after setting CE and before sending * first bit, make this value dependent on dummy cycles. */ - xfer_ll_params.counter_initial_value = 120; - data = nrfe_mspi_xfer_packet.cmd << (BITS_IN_WORD - nrfe_mspi_dev_cfg.cmd_length); - xfer_ll_params.data = (uint8_t *)&data; + xfer_ll_params.counter_initial_value = 32; xfer_ll_params.ce_vio = ce_vios[nrfe_mspi_dev_cfg.ce_num]; - xfer_ll_params.ce_hold = nrfe_mspi_xfer.hold_ce; + xfer_ll_params.ce_hold = true; xfer_ll_params.ce_polarity = nrfe_mspi_dev_cfg.ce_polarity; xfer_ll_params.bit_order = HRT_BO_REVERSED_WORD; - ll_prepare_transfer(xfer_modes.command, nrfe_mspi_dev_cfg.cmd_length); + uint16_t out = nrf_vpr_csr_vio_out_get(); + if (nrfe_mspi_dev_cfg.ce_polarity == MSPI_CE_ACTIVE_LOW) { + out = BIT_SET_VALUE(out, xfer_ll_params.ce_vio, VPRCSR_NORDIC_OUT_HIGH); + } else { + out = BIT_SET_VALUE(out, xfer_ll_params.ce_vio, VPRCSR_NORDIC_OUT_LOW); + } + nrf_vpr_csr_vio_out_set(out); + + /* Send command */ + data = nrfe_mspi_xfer_packet.cmd << (BITS_IN_WORD - nrfe_mspi_xfer.cmd_length); + xfer_ll_params.data = (uint8_t *)&data; + frame_width = set_frame_width_and_pins(xfer_modes.command, MSPI_TX); + + ll_prepare_transfer(frame_width, MSPI_TX, nrfe_mspi_xfer.cmd_length); + + nrf_barrier_rw(); nrf_vpr_clic_int_pending_set(NRF_VPRCLIC, VEVIF_IRQN(HRT_VEVIF_IDX_WRITE)); /* Send address */ - data = nrfe_mspi_xfer_packet.address << (BITS_IN_WORD - nrfe_mspi_dev_cfg.addr_length); + data = nrfe_mspi_xfer_packet.address << (BITS_IN_WORD - nrfe_mspi_xfer.addr_length); xfer_ll_params.data = (uint8_t *)&data; + frame_width = set_frame_width_and_pins(xfer_modes.address, MSPI_TX); + + ll_prepare_transfer(frame_width, MSPI_TX, nrfe_mspi_xfer.addr_length); - ll_prepare_transfer(xfer_modes.address, nrfe_mspi_dev_cfg.addr_length); + nrf_barrier_rw(); nrf_vpr_clic_int_pending_set(NRF_VPRCLIC, VEVIF_IRQN(HRT_VEVIF_IDX_WRITE)); /* Send data */ xfer_ll_params.bit_order = HRT_BO_REVERSED_BYTE; - /* TODO: Jira ticket: NRFX-6876 use read buffer that is appended to packet in NRFE_MSPI_TXRX, - * this is not possible now due to alignment problems + xfer_ll_params.ce_hold = nrfe_mspi_xfer.hold_ce; + /* TODO: Jira ticket: NRFX-6876 use read buffer that is appended to packet in + * NRFE_MSPI_TXRX, this is not possible now due to alignment problems */ - xfer_ll_params.data = nrfe_mspi_xfer_packet.data_buf; + xfer_ll_params.data = buffer; + frame_width = set_frame_width_and_pins(xfer_modes.data, MSPI_TX); + + ll_prepare_transfer(frame_width, MSPI_TX, data_length * BITS_IN_BYTE); - ll_prepare_transfer(xfer_modes.data, nrfe_mspi_xfer_packet.num_bytes * BITS_IN_BYTE); + nrf_barrier_rw(); nrf_vpr_clic_int_pending_set(NRF_VPRCLIC, VEVIF_IRQN(HRT_VEVIF_IDX_WRITE)); + + nrf_barrier_rw(); } -static void process_packet(const void *data, size_t len) +void prepare_and_read_data(uint8_t *buffer, uint32_t data_length) { + NRFX_ASSERT(nrfe_mspi_dev_cfg.ce_num < ce_vios_count); + + struct xfer_io_mode_cfg xfer_modes = get_io_modes(nrfe_mspi_dev_cfg.io_mode); + uint32_t data; + uint16_t out; + uint16_t frame_width; + + /* TODO: Jira ticket: NRFX-6703 + * Device waits this time after setting CE and before sending + * first bit, make this value dependent on dummy cycles. + */ + xfer_ll_params.counter_initial_value = 32; + xfer_ll_params.ce_vio = ce_vios[nrfe_mspi_dev_cfg.ce_num]; + xfer_ll_params.ce_hold = true; + xfer_ll_params.ce_polarity = nrfe_mspi_dev_cfg.ce_polarity; + xfer_ll_params.bit_order = HRT_BO_REVERSED_WORD; + + out = nrf_vpr_csr_vio_out_get(); + + if (nrfe_mspi_dev_cfg.ce_polarity == MSPI_CE_ACTIVE_LOW) { + out = BIT_SET_VALUE(out, xfer_ll_params.ce_vio, VPRCSR_NORDIC_OUT_HIGH); + } else { + out = BIT_SET_VALUE(out, xfer_ll_params.ce_vio, VPRCSR_NORDIC_OUT_LOW); + } + nrf_vpr_csr_vio_out_set(out); + + /* Send command */ + data = nrfe_mspi_xfer_packet.cmd << (BITS_IN_WORD - nrfe_mspi_xfer.cmd_length); + xfer_ll_params.data = (uint8_t *)&data; + frame_width = set_frame_width_and_pins(xfer_modes.command, MSPI_TX); + + ll_prepare_transfer(frame_width, MSPI_TX, nrfe_mspi_xfer.cmd_length); + + nrf_barrier_rw(); + + nrf_vpr_clic_int_pending_set(NRF_VPRCLIC, VEVIF_IRQN(HRT_VEVIF_IDX_WRITE)); + + /* Send address */ + data = nrfe_mspi_xfer_packet.address << (BITS_IN_WORD - nrfe_mspi_xfer.addr_length); + xfer_ll_params.data = (uint8_t *)&data; + frame_width = set_frame_width_and_pins(xfer_modes.address, MSPI_TX); + + ll_prepare_transfer(frame_width, MSPI_TX, nrfe_mspi_xfer.addr_length); + + nrf_barrier_rw(); + + nrf_vpr_clic_int_pending_set(NRF_VPRCLIC, VEVIF_IRQN(HRT_VEVIF_IDX_WRITE)); + + /* Read data */ + xfer_ll_params.bit_order = HRT_BO_REVERSED_BYTE; + xfer_ll_params.ce_hold = nrfe_mspi_xfer.hold_ce; + /* TODO: Jira ticket: NRFX-6876 use read buffer that is appended to packet in + * NRFE_MSPI_TXRX, this is not possible now due to alignment problems + */ + xfer_ll_params.rx_data = buffer; + frame_width = set_frame_width_and_pins(xfer_modes.data, MSPI_RX); + + ll_prepare_receive(frame_width, MSPI_RX, data_length * BITS_IN_BYTE); + + nrf_barrier_rw(); + + nrf_vpr_clic_int_pending_set(NRF_VPRCLIC, VEVIF_IRQN(HRT_VEVIF_IDX_READ)); + + nrf_barrier_rw(); +} + +static void process_packet(const void *data, size_t len, void *priv) +{ + (void)priv; (void)len; + uint16_t dir; uint16_t out; nrfe_mspi_flpr_response_t response; + uint8_t opcode = *(uint8_t *)data; + uint32_t num_bytes = 0; + + printf("opcode: %d\n", opcode); switch (opcode) { case NRFE_MSPI_CONFIG_PINS: { @@ -463,30 +611,48 @@ static void process_packet(const void *data, size_t len) if (pin_number >= sizeof(pin_to_vio_map)) { /* TODO: Jira ticket: NRFX-6875 error*/ - return; + printf("Invalid pin number: %d\n", pin_number); + break; } dir = BIT_SET_VALUE(dir, pin_to_vio_map[pin_number], VPRCSR_NORDIC_DIR_OUTPUT); - if ((fun >= NRF_FUN_SDP_MSPI_CS0) && (fun <= NRF_FUN_SDP_MSPI_CS4)) { + if (fun == NRF_FUN_SDP_MSPI_SCK) { + + NRFX_ASSERT(pin_number < sizeof(pin_to_vio_map)) + clk_vio = pin_to_vio_map[pin_number]; + printf("clk pin %d => vio: %d\n", pin_number, pin_to_vio_map[pin_number]); + } else if ((fun >= NRF_FUN_SDP_MSPI_CS0) && (fun <= NRF_FUN_SDP_MSPI_CS4)) { NRFX_ASSERT(pin_number < sizeof(pin_to_vio_map)) ce_vios[ce_vios_count] = pin_to_vio_map[pin_number]; + + // printf("fun: %d, pin_number: %d, CE_VIO[%d]: %d,\n", fun, + // pin_number, ce_vios[ce_vios_count], pin_to_vio_map[pin_number]); + ce_vios_count++; - /* TODO: Jira ticket: NRFX-6876 Get CE disabled states and set them, - * they need to be passed from app - */ } else if ((fun >= NRF_FUN_SDP_MSPI_DQ0) && (fun <= NRF_FUN_SDP_MSPI_DQ7)) { NRFX_ASSERT(pin_number < sizeof(pin_to_vio_map)) data_vios[data_vios_count] = pin_to_vio_map[pin_number]; + + // printf("fun: %d, pin_number: %d, DATA_VIO[%d]: %d,\n", fun, + // pin_number, data_vios[data_vios_count], + // pin_to_vio_map[pin_number]); + data_vios_count++; } } nrf_vpr_csr_vio_dir_set(dir); nrf_vpr_csr_vio_out_set(0); + + /* Default set CS to HIGH state */ + for (uint8_t i = 0; i < ce_vios_count; i++) { + out = BIT_SET_VALUE(out, ce_vios[i], VPRCSR_NORDIC_OUT_HIGH); + } + break; } case NRFE_MSPI_CONFIG_CTRL: { @@ -494,14 +660,19 @@ static void process_packet(const void *data, size_t len) response.opcode = cfg->opcode; nrfe_mspi_cfg = cfg->cfg; + break; } case NRFE_MSPI_CONFIG_DEV: { nrfe_mspi_dev_cfg_t *cfg = (nrfe_mspi_dev_cfg_t *)data; + response.opcode = cfg->opcode; nrfe_mspi_dev_cfg = cfg->cfg; + nrfe_mspi_dev_cfg.cmd_length *= BITS_IN_BYTE; + nrfe_mspi_dev_cfg.addr_length *= BITS_IN_BYTE; + + dev_pins_configure(nrfe_mspi_dev_cfg.cpp); - configure_clock(nrfe_mspi_dev_cfg.cpp); break; } case NRFE_MSPI_CONFIG_XFER: { @@ -509,6 +680,13 @@ static void process_packet(const void *data, size_t len) response.opcode = xfer->opcode; nrfe_mspi_xfer = xfer->xfer; + nrfe_mspi_xfer.cmd_length *= BITS_IN_BYTE; + nrfe_mspi_xfer.addr_length *= BITS_IN_BYTE; + + printf("CONFIG_XFER: cmd_length: %d, addr_length: %d, tx_dummy: %d, rx_dummy: %d, ce_hold: %d\n", + nrfe_mspi_xfer.cmd_length, nrfe_mspi_xfer.addr_length, + nrfe_mspi_xfer.tx_dummy, nrfe_mspi_xfer.rx_dummy, nrfe_mspi_xfer.hold_ce); + break; } case NRFE_MSPI_TX: @@ -517,20 +695,38 @@ static void process_packet(const void *data, size_t len) response.opcode = packet->opcode; nrfe_mspi_xfer_packet = packet->packet; - - if (packet->packet.dir == MSPI_RX) { - /* TODO: Jira ticket: NRFX-6877 Process received data */ - } else if (packet->packet.dir == MSPI_TX) { - prepare_and_send_data(); + num_bytes = nrfe_mspi_xfer_packet.num_bytes; + + printf("%s cmd: 0x%x, addr: 0x%x, data: %d bytes, cmd_length: %d, " + "addr_length: %d\n", + nrfe_mspi_xfer_packet.dir == MSPI_RX ? "RX" : "TX", + nrfe_mspi_xfer_packet.cmd, nrfe_mspi_xfer_packet.address, + nrfe_mspi_xfer_packet.num_bytes, nrfe_mspi_xfer.cmd_length, + nrfe_mspi_xfer.addr_length); + + if (nrfe_mspi_xfer_packet.dir == MSPI_RX) { + if (nrfe_mspi_xfer_packet.num_bytes > 0) { + prepare_and_read_data(rx_buffer, nrfe_mspi_xfer_packet.num_bytes); + } + } else if (nrfe_mspi_xfer_packet.dir == MSPI_TX) { + // packet++; + // prepare_and_send_data((uint8_t *)packet, num_bytes); + prepare_and_send_data(nrfe_mspi_xfer_packet.data_buf, num_bytes); + } else { + printf("Invalid transfer direction: %d\n", nrfe_mspi_xfer_packet.dir); } break; } default: - response.opcode = NRFE_MSPI_WRONG_OPCODE; + opcode = NRFE_MSPI_WRONG_OPCODE; break; } - ipc_service_send(&ep, (const void *)&response.opcode, sizeof(response)); + uint8_t response_buffer[sizeof(opcode) + num_bytes]; + response_buffer[0] = opcode; + memcpy(&response_buffer[1], rx_buffer, num_bytes); + + ipc_service_send(&ep, (const void *)response_buffer, sizeof(response_buffer)); } static int backend_init(void) @@ -539,11 +735,10 @@ static int backend_init(void) const struct device *ipc0_instance; volatile uint32_t delay = 0; struct ipc_ept_cfg ep_cfg = { - .cb = - { - .bound = ep_bound, - .received = ep_recv, - }, + .cb = { + .bound = ep_bound, + .received = process_packet, + }, }; #if !defined(CONFIG_SYS_CLOCK_EXISTS) diff --git a/drivers/mspi/mspi_nrfe.c b/drivers/mspi/mspi_nrfe.c index 8a19cc5d8c95..f60a801f06fc 100644 --- a/drivers/mspi/mspi_nrfe.c +++ b/drivers/mspi/mspi_nrfe.c @@ -15,7 +15,7 @@ #include #endif #include -LOG_MODULE_REGISTER(mspi_nrfe, CONFIG_MSPI_LOG_LEVEL); +LOG_MODULE_REGISTER(mspi_nrfe, LOG_LEVEL_DBG); #include #include @@ -183,7 +183,8 @@ static void ipc_recv_clbk(const void *data, size_t len) } } - LOG_DBG("Received msg with opcode: %d", response->opcode); +// LOG_DBG("Received msg with opcode: %d", response->opcode); + LOG_HEXDUMP_DBG((uint8_t *)data, len, "RX IPC data:"); } /** @@ -392,6 +393,12 @@ static int api_config(const struct mspi_dt_spec *spec) return ret; } + LOG_DBG("channel_num %d, op_mode %d, duplex %d, dqs_support %d, sw_multi_periph %d,\n ce_group %p, num_ce_gpios %d, num_periph %d, max_freq %d, re_init %d", + config->channel_num, config->op_mode, config->duplex, + config->dqs_support, config->sw_multi_periph, config->ce_group, + config->num_ce_gpios, config->num_periph, config->max_freq, + config->re_init); + /* Send controller configuration to FLPR */ return send_config(NRFE_MSPI_CONFIG_CTRL, (const void *)config, sizeof(struct mspi_cfg)); @@ -482,6 +489,9 @@ static int api_dev_config(const struct device *dev, const struct mspi_dev_id *de memcpy((void *)&drv_data->dev_cfg, (void *)cfg, sizeof(drv_data->dev_cfg)); drv_data->dev_id = *dev_id; + LOG_DBG("io_mode: %d, rx_dummy: %d, tx_dummy: %d, read_cmd: 0x%x, write_cmd: 0x%x,\ncmd_length: %d, addr_length: %d, freq: %d", + cfg->io_mode, cfg->rx_dummy, cfg->tx_dummy, cfg->read_cmd, cfg->write_cmd, cfg->cmd_length, cfg->addr_length, cfg->freq); + return send_config(NRFE_MSPI_CONFIG_DEV, (void *)cfg, sizeof(struct mspi_dev_cfg)); } @@ -514,6 +524,10 @@ static int xfer_packet(struct mspi_xfer_packet *packet, uint32_t timeout) memcpy((void *)&buffer[1], (void *)packet, struct_size); memcpy((void *)(&buffer[1] + struct_size), (void *)packet->data_buf, packet->num_bytes); + LOG_DBG("%s packet cmd: 0x%x, addr: 0x%x, size: %d", packet->dir == MSPI_RX ? "RX" : "TX", + packet->cmd, packet->address, packet->num_bytes); + LOG_HEXDUMP_DBG(packet->data_buf, packet->num_bytes, "Packet data:"); + rc = mspi_ipc_data_send(opcode, buffer, len); if (rc < 0) { LOG_ERR("%d: Packet transfer error: %d", __LINE__, rc); @@ -600,6 +614,11 @@ static int api_transceive(const struct device *dev, const struct mspi_dev_id *de drv_data->xfer = *req; + LOG_DBG("async: %d, xfer_mode: %d, tx_dummy: %d, rx_dummy: %d, cmd_length: %d, addr_length: %d,\nhold_ce: %d, priority: %d, packets: %p, num_packet: %d, timeout: %d", + req->async, req->xfer_mode, req->tx_dummy, req->rx_dummy, + req->cmd_length, req->addr_length, req->hold_ce, req->priority, + req->packets, req->num_packet, req->timeout); + rc = send_config(NRFE_MSPI_CONFIG_XFER, (void *)&drv_data->xfer, sizeof(struct mspi_xfer)); if (rc < 0) { LOG_ERR("Send xfer config error: %d", rc); diff --git a/include/drivers/mspi/nrfe_mspi.h b/include/drivers/mspi/nrfe_mspi.h index a2d8e6ce1635..1065d73e6f30 100644 --- a/include/drivers/mspi/nrfe_mspi.h +++ b/include/drivers/mspi/nrfe_mspi.h @@ -25,7 +25,7 @@ extern "C" { #define NRFE_MSPI_DQ5_PIN_NUMBER 6 #define NRFE_MSPI_DQ6_PIN_NUMBER 7 #define NRFE_MSPI_DQ7_PIN_NUMBER 8 -#define NRFE_MSPI_CS0_PIN_NUMBER 9 +#define NRFE_MSPI_CS0_PIN_NUMBER 5 #define NRFE_MSPI_PINS_MAX 10 #else diff --git a/snippets/sdp/mspi/app.conf b/snippets/sdp/mspi/app.conf index 0bf532300b85..a47e24f21578 100644 --- a/snippets/sdp/mspi/app.conf +++ b/snippets/sdp/mspi/app.conf @@ -2,3 +2,11 @@ CONFIG_MSPI=y CONFIG_MBOX=y CONFIG_IPC_SERVICE=y CONFIG_IPC_SERVICE_BACKEND_ICMSG=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_STDOUT_CONSOLE=y +CONFIG_PRINTK=y +CONFIG_EARLY_CONSOLE=y + +# additional compiler flags +CONFIG_COMPILER_OPT="-fshort-enums" diff --git a/snippets/sdp/mspi/soc/nrf54l15_cpuapp.overlay b/snippets/sdp/mspi/soc/nrf54l15_cpuapp.overlay index c2630b8a2bbe..eb41cfb40f4b 100644 --- a/snippets/sdp/mspi/soc/nrf54l15_cpuapp.overlay +++ b/snippets/sdp/mspi/soc/nrf54l15_cpuapp.overlay @@ -4,32 +4,31 @@ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause */ -/ { + / { soc { reserved-memory { #address-cells = <1>; #size-cells = <1>; - cpuflpr_code_partition: image@17a000 { - reg = <0x17a000 DT_SIZE_K(12)>; + cpuflpr_code_partition: image@178000 { + reg = <0x178000 DT_SIZE_K(20)>; }; - sram_rx: memory@2003c000 { - reg = <0x2003c000 0x0800>; + sram_rx: memory@2003a000 { + reg = <0x2003a000 0x0800>; }; - sram_tx: memory@2003c800 { - reg = <0x2003c800 0x0800>; + sram_tx: memory@2003a800 { + reg = <0x2003a800 0x0800>; }; }; - - cpuflpr_sram_code_data: memory@2003d000 { + cpuflpr_sram_code_data: memory@2003b000 { compatible = "mmio-sram"; - reg = <0x2003d000 DT_SIZE_K(12)>; + reg = <0x2003b000 DT_SIZE_K(20)>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x2003d000 0x3000>; + ranges = <0x0 0x2003b000 0x5000>; }; }; @@ -46,12 +45,12 @@ }; &cpuapp_rram { - reg = <0x0 DT_SIZE_K(1512)>; + reg = <0x0 DT_SIZE_K(1504)>; }; &cpuapp_sram { - reg = <0x20000000 DT_SIZE_K(244)>; - ranges = <0x0 0x20000000 0x3d000>; + reg = <0x20000000 DT_SIZE_K(232)>; + ranges = <0x0 0x20000000 0x3a000>; }; &cpuflpr_vpr { @@ -78,13 +77,8 @@ , , , - , - , - , - , - , - ; - nordic,drive-mode = ; + ; + nordic,drive-mode = ; }; }; /omit-if-no-ref/ sdp_mspi_sleep: sdp_mspi_sleep { @@ -93,21 +87,43 @@ , , , - , - , - , - , - , - ; + ; low-power-enable; }; }; }; +/delete-node/ &mx25r64; + &sdp_mspi { clock-frequency = ; pinctrl-0 = <&sdp_mspi_default>; pinctrl-1 = <&sdp_mspi_sleep>; pinctrl-names = "default", "sleep"; status = "okay"; + mx25r64: mx25r6435f@0 { + compatible = "jedec,mspi-nor", "zephyr,mspi-emul-device"; + status = "okay"; + reg = <0>; + jedec-id = [c2 28 17]; + sfdp-bfp = [ + e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff + ]; + size = <67108864>; + has-dpd; + t-enter-dpd = <10000>; + t-exit-dpd = <35000>; + reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + + mspi-max-frequency = ; + mspi-io-mode = "MSPI_IO_MODE_SINGLE"; + mspi-data-rate = "MSPI_DATA_RATE_SINGLE"; + mspi-hardware-ce-num = <0>; + mspi-cpp-mode = "MSPI_CPP_MODE_0"; + mspi-endian = "MSPI_BIG_ENDIAN"; + mspi-ce-polarity = "MSPI_CE_ACTIVE_LOW"; + }; };