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applications: sdp: mspi: Add RX path to SDP MSPI
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Add RX path to SDP MSPI FLPR app implementation

Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
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@jaz1-nordic
jaz1-nordic committed Dec 20, 2024
1 parent 53888e1 commit cde6f9a
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Showing 11 changed files with 686 additions and 171 deletions.
10 changes: 5 additions & 5 deletions applications/sdp/mspi/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -9,11 +9,11 @@ cmake_minimum_required(VERSION 3.20.0)
find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
project(sdp_mspi)

sdp_assembly_generate("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c")
sdp_assembly_check("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c")
sdp_assembly_prepare_install("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c")
# sdp_assembly_generate("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c")
# sdp_assembly_check("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c")
# sdp_assembly_prepare_install("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c")

target_sources(app PRIVATE src/main.c)
target_sources(app PRIVATE src/hrt/hrt.s)
target_sources(app PRIVATE src/hrt/hrt.c)

add_dependencies(app asm_check)
# add_dependencies(app asm_check)
21 changes: 11 additions & 10 deletions applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.conf
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Original file line number Diff line number Diff line change
Expand Up @@ -7,9 +7,9 @@ CONFIG_LOG=n
CONFIG_I2C=n
CONFIG_WATCHDOG=n
CONFIG_GPIO=n
CONFIG_PINCTRL=n
CONFIG_PINCTRL=y
CONFIG_SPI=n
CONFIG_SERIAL=n
CONFIG_SERIAL=y
CONFIG_FLASH=n

# Power management
Expand All @@ -18,23 +18,23 @@ CONFIG_PM=n
# Interrupts
CONFIG_DYNAMIC_INTERRUPTS=n
CONFIG_IRQ_OFFLOAD=n
CONFIG_GEN_SW_ISR_TABLE=n
CONFIG_GEN_SW_ISR_TABLE=y

# Memory protection
CONFIG_THREAD_STACK_INFO=n
CONFIG_THREAD_CUSTOM_DATA=n
CONFIG_FPU=n

# Boot
CONFIG_BOOT_BANNER=n
CONFIG_BOOT_BANNER=y
CONFIG_NCS_BOOT_BANNER=n

# Console
CONFIG_CONSOLE=n
CONFIG_UART_CONSOLE=n
CONFIG_STDOUT_CONSOLE=n
CONFIG_PRINTK=n
CONFIG_EARLY_CONSOLE=n
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_STDOUT_CONSOLE=y
CONFIG_PRINTK=y
CONFIG_EARLY_CONSOLE=y

# Build
CONFIG_SIZE_OPTIMIZATIONS=y
Expand All @@ -45,4 +45,5 @@ CONFIG_SYS_CLOCK_EXISTS=n
CONFIG_OUTPUT_DISASSEMBLY=y
CONFIG_COMMON_LIBC_MALLOC=n

CONFIG_COMPILER_OPT="-fshort-enums"
# additional compiler flags
CONFIG_COMPILER_OPT="-fshort-enums"
18 changes: 9 additions & 9 deletions applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay
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Original file line number Diff line number Diff line change
Expand Up @@ -10,12 +10,12 @@
#address-cells = <1>;
#size-cells = <1>;

sram_tx: memory@2003c000 {
reg = <0x2003c000 0x0800>;
sram_tx: memory@2003a000 {
reg = <0x2003a000 0x0800>;
};

sram_rx: memory@2003c800 {
reg = <0x2003c800 0x0800>;
sram_rx: memory@2003a800 {
reg = <0x2003a800 0x0800>;
};
};
};
Expand All @@ -33,16 +33,16 @@
};

&cpuflpr_rram {
reg = <0x17a000 DT_SIZE_K(12)>;
reg = <0x178000 DT_SIZE_K(20)>;
};

&cpuflpr_code_partition {
reg = <0x0 DT_SIZE_K(12)>;
reg = <0x0 DT_SIZE_K(20)>;
};

&cpuflpr_sram {
reg = <0x2003d000 DT_SIZE_K(12)>;
ranges = <0x0 0x2003d000 0x3000>;
reg = <0x2003b000 DT_SIZE_K(20)>;
ranges = <0x0 0x2003b000 0x5000>;
};

&cpuflpr_vevif_rx {
Expand Down Expand Up @@ -85,7 +85,7 @@
};

&uart30 {
status = "disabled";
status = "okay";
};

&pwm20 {
Expand Down
122 changes: 121 additions & 1 deletion applications/sdp/mspi/src/hrt/hrt.c
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@
#include <hal/nrf_vpr_csr_vtim.h>
#include <drivers/mspi/nrfe_mspi.h>
#include <zephyr/drivers/mspi.h>
#include <stdio.h>

void hrt_write(volatile struct hrt_ll_xfer xfer_ll_params)
{
Expand Down Expand Up @@ -100,7 +101,6 @@ void hrt_write(volatile struct hrt_ll_xfer xfer_ll_params)

/* Disable CS */
if (!xfer_ll_params.ce_hold) {

out = nrf_vpr_csr_vio_out_get();

if (xfer_ll_params.ce_polarity == MSPI_CE_ACTIVE_LOW) {
Expand All @@ -114,3 +114,123 @@ void hrt_write(volatile struct hrt_ll_xfer xfer_ll_params)
/* Stop counter */
nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_STOP);
}

void hrt_read(volatile struct hrt_ll_xfer xfer_ll_params)
{
uint16_t out;
uint32_t word_ctr = 0;

NRFX_ASSERT((xfer_ll_params.last_word_clocks != 1) || (xfer_ll_params.words == 1))

/* Enable CS */
out = nrf_vpr_csr_vio_out_get();

if (xfer_ll_params.ce_polarity == MSPI_CE_ACTIVE_LOW) {
out = BIT_SET_VALUE(out, xfer_ll_params.ce_vio, VPRCSR_NORDIC_OUT_LOW);
} else {
out = BIT_SET_VALUE(out, xfer_ll_params.ce_vio, VPRCSR_NORDIC_OUT_HIGH);
}
nrf_vpr_csr_vio_out_set(out);

switch (xfer_ll_params.bit_order) {
case HRT_BO_NORMAL:
nrf_vpr_csr_vio_out_buffered_set(((uint32_t *)xfer_ll_params.data)[word_ctr++]);
break;
case HRT_BO_REVERSED_BYTE:
nrf_vpr_csr_vio_out_buffered_reversed_byte_set(
((uint32_t *)xfer_ll_params.data)[word_ctr++]);
break;
case HRT_BO_REVERSED_WORD:
nrf_vpr_csr_vio_out_buffered_reversed_word_set(
((uint32_t *)xfer_ll_params.data)[word_ctr++]);
break;
}

/* Counter settings */
nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_RELOAD);
nrf_vpr_csr_vtim_count_mode_set(1, NRF_VPR_CSR_VTIM_COUNT_RELOAD);

/* TODO: Jira ticket: NRFX-6703
* Top value of VTIM. This will determine clock frequency
* (SPI_CLOCK ~= CPU_CLOCK / (2 * TOP)).
* Calculate this value based on frequency
*/
nrf_vpr_csr_vtim_simple_counter_top_set(0, 32);
/* Trigger data capture every two clock cycles */
nrf_vpr_csr_vtim_simple_counter_top_set(1, 2 * (32 + 1) - 1);

/* Start both counters */
nrf_vpr_csr_vtim_combined_counter_set(
(32 << VPRCSR_NORDIC_CNT_CNT0_Pos) +
(32 << VPRCSR_NORDIC_CNT_CNT1_Pos));

nrf_vpr_csr_vtim_simple_wait_set(0, false, 0);

while (word_ctr < xfer_ll_params.words) {

switch (xfer_ll_params.bit_order) {
case HRT_BO_NORMAL:
nrf_vpr_csr_vio_out_buffered_set(
((uint32_t *)xfer_ll_params.data)[word_ctr]);
((uint32_t *)xfer_ll_params.rx_data)[word_ctr] =
nrf_vpr_csr_vio_in_buffered_get();
break;
case HRT_BO_REVERSED_BYTE:
nrf_vpr_csr_vio_out_buffered_reversed_byte_set(
((uint32_t *)xfer_ll_params.data)[word_ctr]);
((uint32_t *)xfer_ll_params.rx_data)[word_ctr] =
nrf_vpr_csr_vio_in_buffered_reversed_byte_get();
break;
case HRT_BO_REVERSED_WORD:
nrf_vpr_csr_vio_out_buffered_reversed_word_set(
((uint32_t *)xfer_ll_params.data)[word_ctr]);
((uint32_t *)xfer_ll_params.rx_data)[word_ctr] =
nrf_vpr_csr_vio_in_buffered_get();
break;
}
word_ctr++;
}

nrf_vpr_csr_vio_shift_cnt_out_buffered_set(0);
while (nrf_vpr_csr_vio_shift_cnt_out_get() > 0) {};

if (xfer_ll_params.eliminate_last_pulse) {
nrf_vpr_csr_vtim_simple_wait_set(0, false, 0);
}

nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_STOP);
nrf_vpr_csr_vtim_simple_wait_set(0, false, 0);

switch (xfer_ll_params.bit_order) {
case HRT_BO_NORMAL:
((uint32_t *)xfer_ll_params.rx_data)[word_ctr] = nrf_vpr_csr_vio_in_buffered_get();
break;
case HRT_BO_REVERSED_BYTE:
((uint32_t *)xfer_ll_params.rx_data)[word_ctr] =
nrf_vpr_csr_vio_in_buffered_reversed_byte_get();
break;
case HRT_BO_REVERSED_WORD:
((uint32_t *)xfer_ll_params.rx_data)[word_ctr] = nrf_vpr_csr_vio_in_buffered_get();
break;
}

nrf_vpr_csr_vio_shift_cnt_out_set(0);
nrf_vpr_csr_vio_mode_out_t out_mode = {0};
nrf_vpr_csr_vio_mode_out_set(&out_mode);
nrf_vpr_csr_vio_mode_in_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS);

/* Disable CS */
if (xfer_ll_params.ce_hold == false) {
out = nrf_vpr_csr_vio_out_get();

if (xfer_ll_params.ce_polarity == MSPI_CE_ACTIVE_LOW) {
out = BIT_SET_VALUE(out, xfer_ll_params.ce_vio, VPRCSR_NORDIC_OUT_HIGH);
} else {
out = BIT_SET_VALUE(out, xfer_ll_params.ce_vio, VPRCSR_NORDIC_OUT_LOW);
}
nrf_vpr_csr_vio_out_set(out);
}

/* Stop counters */
nrf_vpr_csr_vtim_count_mode_set(1, NRF_VPR_CSR_VTIM_COUNT_STOP);
}
13 changes: 11 additions & 2 deletions applications/sdp/mspi/src/hrt/hrt.h
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Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,7 @@ struct hrt_ll_xfer {

/** @brief Buffer for RX/TX data */
uint8_t *data;
uint8_t *rx_data;

/** @brief CEIL(buffer_length_bits/32)
*/
Expand Down Expand Up @@ -75,7 +76,7 @@ struct hrt_ll_xfer {
uint8_t ce_vio;

/** @brief If true chip enable pin will be left active after transfer */
uint8_t ce_hold;
bool ce_hold;

/** @brief Chip enable pin polarity in enabled state. */
enum mspi_ce_polarity ce_polarity;
Expand All @@ -88,10 +89,18 @@ struct hrt_ll_xfer {

/** @brief Write.
*
* Function to be used to write data on SPI.
* Function to be used to write data on MSPI.
*
* @param[in] xfer_ll_params Low level transfer parameters.
*/
void hrt_write(volatile struct hrt_ll_xfer xfer_ll_params);

/** @brief Read.
*
* Function to be used to read data from MSPI.
*
* @param[in] xfer_ll_params Low level transfer parameters.
*/
void hrt_read(volatile struct hrt_ll_xfer xfer_ll_params);

#endif /* _HRT_H__ */
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