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<title>PTU CSE Syllabus Guide »3rd Sem</title>
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<h1><a href="index.php" id="logo">..</a> » <a href="3rd-index.php">3rd Sem</a> » <a href="3rd-ca.php">CA</a> » <a href="3rd-ca-syllabus.php">Syllabus</a></h1>
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<P class="p106 ft6"><NOBR>CS-201</NOBR> Computer Architecture.</P>
<TABLE cellpadding=0 cellspacing=0 class="t8">
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<TD class="tr1 td185"><P class="p10 ft21">External Marks:</P></TD>
<TD class="tr1 td101"><P class="p76 ft21">60</P></TD>
<TD class="tr1 td193"><P class="p107 ft21">L</P></TD>
<TD class="tr1 td18"><P class="p108 ft21">T</P></TD>
<TD class="tr1 td189"><P class="p76 ft21">P</P></TD>
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<TR>
<TD class="tr2 td185"><P class="p10 ft12">Internal Marks:</P></TD>
<TD class="tr2 td101"><P class="p109 ft12">40</P></TD>
<TD class="tr2 td193"><P class="p107 ft12">3</P></TD>
<TD class="tr2 td18"><P class="p110 ft12">1</P></TD>
<TD class="tr2 td189"><P class="p42 ft12">-</P></TD>
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<TD class="tr23 td185"><P class="p10 ft6">Total Marks:</P></TD>
<TD class="tr23 td101"><P class="p109 ft6">100</P></TD>
<TD class="tr23 td193"><P class="p10 ft8"> </P></TD>
<TD class="tr23 td18"><P class="p10 ft8"> </P></TD>
<TD class="tr23 td189"><P class="p10 ft8"> </P></TD>
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<P class="p79 ft6">PREREQUISTES <SPAN class="ft5">: None</SPAN></P>
<P class="p80 ft26"><SPAN class="ft12">OBJECTIVES </SPAN>: This course offers a good understanding of the various functional units of a computer system and prepares the student to be in a position to design a basic computer system. Finally the student will be exposed to the recent trends in parallel and distributed computing and multithreaded application.</P>
<P class="p81 ft21">COURSE CONTENTS :</P>
<P class="p82 ft5">Principles of computer design - software / hardware interaction, cost/benefit concept of layers in architecture design 10%]</P>
<P class="p83 ft5">Basic Computer Organization taking 8085 as an example binary arithmetic - add, subtract, multiply - algorithms and implementations. carry look ahead add fast adders. [15%]</P>
<P class="p84 ft5">CPU design - Choice of instruction set control structure hardwired and microprogrammed control - RISC vs CISC, Pipelining in CPU design superscalar machines. [15%]</P>
<P class="p85 ft5">Memory hierarchy design caches, main memory, Interleave memory virtual memory architectural aids in implementing these. [10%]</P>
<P class="p79 ft5">I/O Modes- program interrupt, DMA, Channel, I/O Processor. [15%]</P>
<P class="p86 ft5">I/O performance measures - Buses connecting I/O devices to CPU/memory - interaction with operating system Serial/Parallel Interfaces taking 8251 and 8255 as examples. [15%]</P>
<P class="p86 ft26">Performance evaluation SPEC marks LINPACK Whetstone Dhrystone etc., Transaction processing benchmarks. [10%]</P>
<P class="p87 ft5">Multiprocessors - Parallel & distributed computers - SIMD SPMD and MIMD machines. [10%]</P>
<P class="p88 ft21">TEXT / REFERENCES :</P>
<P class="p89 ft26">Patterson and Hennessy, Computer Architectures, Morgaon Kauffman, San Mateo, CA, USA, 1992.</P>
<P class="p90 ft26">P.Pal Chaudhary, Computer Organization and Design Prentice Hall of India Pvt. Ltd., New Delhi, 1994.</P>
<P class="p91 ft26">P.V.S. Rao, Perspectives in Computer Architecture, Prentice Hall of India Pvt. Ltd., NEW Delhi,1994.</P>
<P class="p92 ft5">M.R. Bhujade, Digital Computer Design Principles, Pitamber Publishing Co., 3rd Edition, 1996.</P>
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