From 798f859ba1735db76f5c47b70e4440ad6569ff51 Mon Sep 17 00:00:00 2001 From: Jared McNeill Date: Mon, 19 Feb 2024 08:01:57 -0400 Subject: [PATCH] ROC-RK3568-PC: Configure and enable UART3 and UART4. The RJ45 management port on the ROC-RK3568-PC is wired to UART3 and UART4, in addition to the console device UART2. Initialize them and add nodes in the DSDT so they can be used by an OS. --- .../Drivers/BoardInitDxe/BoardInitDxe.c | 33 +++++++++++++ .../Firefly/ROC-RK3568-PC/ROC-RK3568-PC.dsc | 4 ++ .../Rockchip/Rk356x/AcpiTables/CM3.inf | 2 + .../Rockchip/Rk356x/AcpiTables/OrangePi3B.inf | 2 + .../Rockchip/Rk356x/AcpiTables/Quartz64.inf | 2 + .../Rk356x/AcpiTables/ROC-RK3566-PC.inf | 2 + .../Rk356x/AcpiTables/ROC-RK3568-PC.inf | 2 + .../Rockchip/Rk356x/AcpiTables/SOQuartz.inf | 2 + .../Rockchip/Rk356x/AcpiTables/Uart.asl | 47 +++++++++++++++++-- .../Silicon/Rockchip/Rk356x/Rk356x.dec | 3 ++ 10 files changed, 96 insertions(+), 3 deletions(-) diff --git a/edk2-rockchip/Platform/Firefly/ROC-RK3568-PC/Drivers/BoardInitDxe/BoardInitDxe.c b/edk2-rockchip/Platform/Firefly/ROC-RK3568-PC/Drivers/BoardInitDxe/BoardInitDxe.c index 4de7d1da2..d61a80ffa 100644 --- a/edk2-rockchip/Platform/Firefly/ROC-RK3568-PC/Drivers/BoardInitDxe/BoardInitDxe.c +++ b/edk2-rockchip/Platform/Firefly/ROC-RK3568-PC/Drivers/BoardInitDxe/BoardInitDxe.c @@ -94,6 +94,9 @@ */ #define GRF_IOFUNC_SEL0 (SYS_GRF + 0x0300) #define GMAC1_IOMUX_SEL BIT8 +#define GRF_IOFUNC_SEL3 (SYS_GRF + 0x030c) +#define UART3_IOMUX_SEL BIT14 +#define UART4_IOMUX_SEL BIT12 #define GRF_IOFUNC_SEL5 (SYS_GRF + 0x0314) #define PCIE30X2_IOMUX_SEL_MASK (BIT7|BIT6) #define PCIE30X2_IOMUX_SEL_M1 BIT6 @@ -156,6 +159,16 @@ STATIC CONST GPIO_IOMUX_CONFIG mPcie30x2IomuxConfig[] = { { "pcie30x2_wakenm1", 2, GPIO_PIN_PD5, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, }; +STATIC CONST GPIO_IOMUX_CONFIG mUart3IomuxConfig[] = { + { "uart3_rxm1", 3, GPIO_PIN_PC0, 4, GPIO_PIN_PULL_UP, GPIO_PIN_DRIVE_DEFAULT }, + { "uart3_txm1", 3, GPIO_PIN_PB7, 4, GPIO_PIN_PULL_UP, GPIO_PIN_DRIVE_DEFAULT }, +}; + +STATIC CONST GPIO_IOMUX_CONFIG mUart4IomuxConfig[] = { + { "uart4_rxm1", 3, GPIO_PIN_PB1, 4, GPIO_PIN_PULL_UP, GPIO_PIN_DRIVE_DEFAULT }, + { "uart4_txm1", 3, GPIO_PIN_PB2, 4, GPIO_PIN_PULL_UP, GPIO_PIN_DRIVE_DEFAULT }, +}; + STATIC VOID BoardInitGmac ( @@ -359,6 +372,23 @@ BoardInitWiFi ( MicroSecondDelay (100000); } +STATIC +VOID +BoardInitUart ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "BOARD: UART init\n")); + + /* Select M1 mux solution for UART3 and UART4 */ + MmioWrite32 (GRF_IOFUNC_SEL3, (UART3_IOMUX_SEL << 16) | UART3_IOMUX_SEL | + (UART4_IOMUX_SEL << 16) | UART4_IOMUX_SEL); + + /* Configure pins */ + GpioSetIomuxConfig (mUart3IomuxConfig, ARRAY_SIZE (mUart3IomuxConfig)); + GpioSetIomuxConfig (mUart4IomuxConfig, ARRAY_SIZE (mUart4IomuxConfig)); +} + EFI_STATUS EFIAPI BoardInitDriverEntryPoint ( @@ -417,5 +447,8 @@ BoardInitDriverEntryPoint ( /* WiFi setup */ BoardInitWiFi (); + /* UART setup */ + BoardInitUart (); + return EFI_SUCCESS; } diff --git a/edk2-rockchip/Platform/Firefly/ROC-RK3568-PC/ROC-RK3568-PC.dsc b/edk2-rockchip/Platform/Firefly/ROC-RK3568-PC/ROC-RK3568-PC.dsc index c0c4ebfc5..54ab9d166 100644 --- a/edk2-rockchip/Platform/Firefly/ROC-RK3568-PC/ROC-RK3568-PC.dsc +++ b/edk2-rockchip/Platform/Firefly/ROC-RK3568-PC/ROC-RK3568-PC.dsc @@ -404,6 +404,10 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterAccessWidth|32 + # UART3 and 4 + gRk356xTokenSpaceGuid.PcdUart3Status|0xF + gRk356xTokenSpaceGuid.PcdUart4Status|0xF + # TODO: Use 1.5M baud gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 diff --git a/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/CM3.inf b/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/CM3.inf index dfc461315..c77f26774 100755 --- a/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/CM3.inf +++ b/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/CM3.inf @@ -60,6 +60,8 @@ gRk356xTokenSpaceGuid.PcdXhc1Status gRk356xTokenSpaceGuid.PcdMac0Status gRk356xTokenSpaceGuid.PcdMac1Status + gRk356xTokenSpaceGuid.PcdUart3Status + gRk356xTokenSpaceGuid.PcdUart4Status gRk356xTokenSpaceGuid.PcdMshc1Status gRk356xTokenSpaceGuid.PcdMshc1SdioIrq diff --git a/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/OrangePi3B.inf b/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/OrangePi3B.inf index 1be617c39..ec461d123 100644 --- a/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/OrangePi3B.inf +++ b/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/OrangePi3B.inf @@ -60,6 +60,8 @@ gRk356xTokenSpaceGuid.PcdXhc1Status gRk356xTokenSpaceGuid.PcdMac0Status gRk356xTokenSpaceGuid.PcdMac1Status + gRk356xTokenSpaceGuid.PcdUart3Status + gRk356xTokenSpaceGuid.PcdUart4Status gRk356xTokenSpaceGuid.PcdMshc1Status gRk356xTokenSpaceGuid.PcdMshc1SdioIrq diff --git a/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/Quartz64.inf b/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/Quartz64.inf index 043df405f..d6aefe9d2 100755 --- a/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/Quartz64.inf +++ b/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/Quartz64.inf @@ -60,6 +60,8 @@ gRk356xTokenSpaceGuid.PcdXhc1Status gRk356xTokenSpaceGuid.PcdMac0Status gRk356xTokenSpaceGuid.PcdMac1Status + gRk356xTokenSpaceGuid.PcdUart3Status + gRk356xTokenSpaceGuid.PcdUart4Status gRk356xTokenSpaceGuid.PcdMshc1Status gRk356xTokenSpaceGuid.PcdMshc1SdioIrq diff --git a/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/ROC-RK3566-PC.inf b/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/ROC-RK3566-PC.inf index ce4573933..18e95129d 100755 --- a/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/ROC-RK3566-PC.inf +++ b/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/ROC-RK3566-PC.inf @@ -60,6 +60,8 @@ gRk356xTokenSpaceGuid.PcdXhc1Status gRk356xTokenSpaceGuid.PcdMac0Status gRk356xTokenSpaceGuid.PcdMac1Status + gRk356xTokenSpaceGuid.PcdUart3Status + gRk356xTokenSpaceGuid.PcdUart4Status gRk356xTokenSpaceGuid.PcdMshc1Status gRk356xTokenSpaceGuid.PcdMshc1SdioIrq diff --git a/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/ROC-RK3568-PC.inf b/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/ROC-RK3568-PC.inf index ea373c490..f21f3766e 100755 --- a/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/ROC-RK3568-PC.inf +++ b/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/ROC-RK3568-PC.inf @@ -60,6 +60,8 @@ gRk356xTokenSpaceGuid.PcdXhc1Status gRk356xTokenSpaceGuid.PcdMac0Status gRk356xTokenSpaceGuid.PcdMac1Status + gRk356xTokenSpaceGuid.PcdUart3Status + gRk356xTokenSpaceGuid.PcdUart4Status gRk356xTokenSpaceGuid.PcdMshc1Status gRk356xTokenSpaceGuid.PcdMshc1SdioIrq diff --git a/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/SOQuartz.inf b/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/SOQuartz.inf index 1ae97d0f4..14b247c41 100755 --- a/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/SOQuartz.inf +++ b/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/SOQuartz.inf @@ -60,6 +60,8 @@ gRk356xTokenSpaceGuid.PcdXhc1Status gRk356xTokenSpaceGuid.PcdMac0Status gRk356xTokenSpaceGuid.PcdMac1Status + gRk356xTokenSpaceGuid.PcdUart3Status + gRk356xTokenSpaceGuid.PcdUart4Status gRk356xTokenSpaceGuid.PcdMshc1Status gRk356xTokenSpaceGuid.PcdMshc1SdioIrq diff --git a/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/Uart.asl b/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/Uart.asl index c757d0694..1fc1db976 100755 --- a/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/Uart.asl +++ b/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/Uart.asl @@ -8,11 +8,12 @@ #include -// UART DW APB -Device (COM0) { +// UART2 DW APB +Device (URT2) { Name (_HID, "HISI0031") Name (_CID, "8250dw"); - Name (_UID, Zero) + Name (_UID, 2) + Name (_STA, 0xF) Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, FixedPcdGet64 (PcdSerialRegisterBase), @@ -27,4 +28,44 @@ Device (COM0) { Package () { "reg-io-width", 4 }, } }) +} + +// UART3 DW APB +Device (URT3) { + Name (_HID, "HISI0031") + Name (_CID, "8250dw"); + Name (_UID, 3) + Name (_STA, FixedPcdGet8(PcdUart3Status)) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFE670000, 0x0001000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 151 } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", FixedPcdGet32 (PcdSerialClockRate) }, + Package () { "reg-shift", 2 }, + Package () { "reg-io-width", 4 }, + } + }) +} + +// UART4 DW APB +Device (URT4) { + Name (_HID, "HISI0031") + Name (_CID, "8250dw"); + Name (_UID, 4) + Name (_STA, FixedPcdGet8(PcdUart4Status)) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFE680000, 0x0001000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 152 } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", FixedPcdGet32 (PcdSerialClockRate) }, + Package () { "reg-shift", 2 }, + Package () { "reg-io-width", 4 }, + } + }) } \ No newline at end of file diff --git a/edk2-rockchip/Silicon/Rockchip/Rk356x/Rk356x.dec b/edk2-rockchip/Silicon/Rockchip/Rk356x/Rk356x.dec index 443bbe464..b23f430cf 100644 --- a/edk2-rockchip/Silicon/Rockchip/Rk356x/Rk356x.dec +++ b/edk2-rockchip/Silicon/Rockchip/Rk356x/Rk356x.dec @@ -80,3 +80,6 @@ gRk356xTokenSpaceGuid.PcdCpuVoltageUVolBase|600000|UINT32|0x00000083 gRk356xTokenSpaceGuid.PcdCpuVoltageUVolStep|6250|UINT32|0x00000084 gRk356xTokenSpaceGuid.PcdCpuVoltageRampDelay|2300|UINT32|0x00000085 + # Pcds for UART + gRk356xTokenSpaceGuid.PcdUart3Status|0|UINT8|0x00000090 + gRk356xTokenSpaceGuid.PcdUart4Status|0|UINT8|0x00000091 \ No newline at end of file