Design a 5-stage PipeLined digital system that will compute the remainder
C = A mod B
- the number A in the range from 0 to 255 (i.e., an 8-bit unsigned number)
- the number B in the range from 8 to 15 (i.e., a 4-bit unsigned number with the most significant bit set to 1).
- You are not allowed to use the following operators ( mod,/,*)
- Clock
- Reset (1 → asynchronous and set all registers to value of 0)
- A : 8-bits input read at each rising edge of the clock
- B : 4-bits input read at each rising edge of the clock
- Start : 1 → the system will start computation.
0 → the system will stop receiving inputs (the operations in the pipe will continue till they finish)
- C : 4-bits output represents the reminder
- The First remainder value is generated after 4 clock cycles (at the 5th rising edge).
- The rest of the results should be generated at the 6,7,8,9, ….etc. (like any normal pipeline).
- Done: is raised to One when a valid output is generated, else 0.
- Err : is raised to One if B value is smaller than 8 else 0
A_reg = A
B_reg = B*2^24
for i = 0 to 5
{
if(A_reg > B_reg)
{
A_reg = A_reg - B_reg
}
B_reg = B_reg >> 1
}
C = A_reg[3 downto 0]