test: initlize itlbmem and fix test dependency (#13)

* test: remove all debug comments and initlize itlbmem

* build: add special test config use chisel3.5.4

* ci: add cross publish and test with scala2.12.15

---------

Co-authored-by: SeddonShen <283481855@qq.com>

.github/workflows/CI.yml

@@ -23,7 +23,7 @@ jobs:
       - name: Setup GPG (for Publish)
         uses: olafurpg/setup-gpg@v3
       - name: Publish
-        run: sbt ci-release
+        run: sbt +ci-release
         env:
           PGP_PASSPHRASE: ${{ secrets.PGP_PASSPHRASE }}
           PGP_SECRET: ${{ secrets.PGP_SECRET }}

.github/workflows/Test.yml

@@ -16,4 +16,4 @@ jobs:
       - name: Cache Scala
         uses: coursier/cache-action@v5
       - name: SBT Test
-        run: sbt test
+        run: sbt "++ 2.12.15! test"

build.sbt

@@ -1,6 +1,8 @@
 ThisBuild / version      := "1.1-SNAPSHOT"
 ThisBuild / organization := "cn.ac.ios.tis"
-ThisBuild / scalaVersion := "2.13.10"
+ThisBuild / scalaVersion := "2.13.8"
+
+ThisBuild / crossScalaVersions := Seq("2.12.15", "2.13.8", "2.13.10")
 
 resolvers ++= Seq(
   Resolver.sonatypeRepo("snapshots"),
@@ -33,14 +35,22 @@ lazy val root = (project in file("."))
   .settings(
     name := "RiscvSpecCore",
     libraryDependencies ++= Seq(
-      "edu.berkeley.cs" %% "chisel3"    % "3.6.0",
-      "edu.berkeley.cs" %% "chiseltest" % "0.6.2" % "test"
+      "edu.berkeley.cs" %% "chisel3" % "3.6.0"
     ),
     scalacOptions ++= Seq(
       "-language:reflectiveCalls",
       "-deprecation",
       "-feature",
       "-Xcheckinit"
     ),
-    addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.6.0" cross CrossVersion.full)
+    addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.6.0" cross CrossVersion.full),
+    // special test configuration to avoid bug in chisel3.6
+    // use `sbt "++ 2.12.15! test"` to run tests, should finish in 15 minutes
+    dependencyOverrides ++= Seq(
+      "edu.berkeley.cs" %% "chisel3" % "3.5.4" % "test",
+      compilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.5.4" % "test" cross CrossVersion.full)
+    ),
+    libraryDependencies ++= Seq(
+      "edu.berkeley.cs" %% "chiseltest" % "0.5.4" % "test"
+    )
   )

src/main/scala/rvspeccore/core/RiscvCore.scala

@@ -91,8 +91,8 @@ class RiscvCore()(implicit config: RVConfig) extends BaseCore with RVInstSet {
   tlb := 0.U.asTypeOf(new TLBIO)
   // ID & EXE
   when(io.valid) {
-    printf("PC: %x Inst:%x io.PC:%x \n", now.pc, inst, io.now.pc)
-    printf("io.mem.read.valid:%x addr:%x data:%x\n", io.mem.read.valid, io.mem.read.addr, io.mem.read.data)
+    // printf("PC: %x Inst:%x io.PC:%x \n", now.pc, inst, io.now.pc)
+    // printf("io.mem.read.valid:%x addr:%x data:%x\n", io.mem.read.valid, io.mem.read.addr, io.mem.read.data)
     // when(now.pc(1,0) =/= "b00".U & !now.csr.misa(CSR.getMisaExtInt('C'))){
     //   raiseException(0)
     //   next.csr.mtval := now.pc
@@ -103,7 +103,7 @@ class RiscvCore()(implicit config: RVConfig) extends BaseCore with RVInstSet {
     when(resultStatus){
       inst := io.inst
     }.otherwise{
-      printf("[Debug]iFetch Fail and Give NOP:")
+      // printf("[Debug]iFetch Fail and Give NOP:")
       inst := 0.U(XLEN.W) // With a NOP instruction
     }
     iFetchpc := resultPC

src/main/scala/rvspeccore/core/spec/instset/IBase.scala

@@ -128,7 +128,9 @@ trait IBase extends BaseCore with CommonDecode with IBaseInsts with ExceptionSup
 
   }
   def addrAligned(size: UInt, addr: UInt): Bool = {
-      MuxLookup(size, false.B)(
+      MuxLookup(
+        size,
+        false.B,
         Seq(
           "b00".U   -> true.B,              //b
           "b01".U   -> (addr(0)   === 0.U), //h
@@ -161,8 +163,7 @@ trait IBase extends BaseCore with CommonDecode with IBaseInsts with ExceptionSup
   def getfetchSize():UInt = {
     MuxLookup(
       now.csr.misa(CSR.getMisaExtInt('C')),
-      SizeOp.w
-    )(
+      SizeOp.w,
       Seq(
         "b0".U   -> SizeOp.w,
         "b1".U   -> SizeOp.h
@@ -289,7 +290,7 @@ trait IBase extends BaseCore with CommonDecode with IBaseInsts with ExceptionSup
       }
     }
     when(LH(inst))  { 
-      printf("[Debug]LH Begin: Reg%x:%x %x %x\n",rs1,now.reg(rs1),imm,rd)
+      // printf("[Debug]LH Begin: Reg%x:%x %x %x\n",rs1,now.reg(rs1),imm,rd)
       decodeI; 
       when(addrAligned(SizeOp.h, now.reg(rs1) + imm)){
         next.reg(rd) := signExt(memRead(now.reg(rs1) + imm, 16.U)(15, 0), XLEN) 
@@ -298,18 +299,18 @@ trait IBase extends BaseCore with CommonDecode with IBaseInsts with ExceptionSup
         raiseException(MExceptionCode.loadAddressMisaligned)
       }
       // alignedException("Load", SizeOp.h, now.reg(rs1) + imm); 
-      printf("[Debug]LH End: %x\n",next.reg(rd))
+      // printf("[Debug]LH End: %x\n",next.reg(rd))
     }
     when(LW(inst))  { 
-      printf("[Debug]LW Begin: Reg:%x, Addr: %x TargetReg: %x\n",rs1,now.reg(rs1) + imm,rd)
+      // printf("[Debug]LW Begin: Reg:%x, Addr: %x TargetReg: %x\n",rs1,now.reg(rs1) + imm,rd)
       decodeI; 
       when(addrAligned(SizeOp.w, now.reg(rs1) + imm)){
         next.reg(rd) := signExt(memRead(now.reg(rs1) + imm, 32.U)(31, 0), XLEN) 
       }.otherwise{
         mem.read.addr := now.reg(rs1) + imm
         raiseException(MExceptionCode.loadAddressMisaligned)
       }
-      printf("[Debug]LW End: %x\n", next.reg(rd))
+      // printf("[Debug]LW End: %x\n", next.reg(rd))
     }
     when(LBU(inst)) { decodeI; alignedException("Load", SizeOp.b, rs2); next.reg(rd) := zeroExt(memRead(now.reg(rs1) + imm, 8.U)(7, 0), XLEN) }
     when(LHU(inst)) { 
@@ -344,7 +345,7 @@ trait IBase extends BaseCore with CommonDecode with IBaseInsts with ExceptionSup
     when(EBREAK(inst)) {
       decodeI;
       raiseException(MExceptionCode.breakpoint)
-      printf("IS EBREAK\n")
+      // printf("IS EBREAK\n")
     }
 
     when(ECALL(inst)) {
@@ -354,7 +355,7 @@ trait IBase extends BaseCore with CommonDecode with IBaseInsts with ExceptionSup
         is(0x1.U) { raiseException(MExceptionCode.environmentCallFromSmode) }
         is(0x0.U) { raiseException(MExceptionCode.environmentCallFromUmode) }
       }
-      printf("IS ECALL\n")
+      // printf("IS ECALL\n")
     }
     when(FENCE(inst)) {
       decodeI /* then do nothing for now */

src/main/scala/rvspeccore/core/spec/instset/Priviledged.scala

@@ -41,20 +41,20 @@ trait PriviledgedExtension extends BaseCore with CommonDecode with PriviledgedIn
   def doRVPriviledged()(implicit config: RVConfig): Unit = {
     // FIXME: need to decode more insts & clearify there actions(not do nothing....)
     when(SRET(inst)) { 
-      printf("Is SRET:%x\n",inst)
+      // printf("Is SRET:%x\n",inst)
       decodeI 
        Sret()
       /* then do nothing for now */ 
     }
     when(MRET(inst)) { 
-      printf("Is MRET:%x\n",inst)
+      // printf("Is MRET:%x\n",inst)
       decodeI
       Mret()
       /* then do nothing for now */ 
     }
     when(WFI(inst)) { decodeI /* then do nothing for now */ }
     when(NOP(inst)) { 
-      printf("Is NOP:%x\n",inst)
+      // printf("Is NOP:%x\n",inst)
       tryRaiseException()
       /* then do nothing for now */ 
     }

src/main/scala/rvspeccore/core/spec/instset/ZicsrExtension.scala

@@ -53,7 +53,7 @@ trait ZicsrExtension extends BaseCore with CommonDecode with ZicsrExtensionInsts
     val isIllegalMode  = priviledgeMode < addr(9, 8)
     // val isIllegalWrite = wen && (addr(11, 10) === "b11".U) && !justRead  // Write a read-only CSR register
     val isIllegalAccess = isIllegalMode || isIllegalWrite
-    val has:       Bool = MuxLookup(addr, false.B)(now.csr.table.map { x => x.info.addr -> true.B })
+    val has:       Bool = MuxLookup(addr, false.B, now.csr.table.map { x => x.info.addr -> true.B })
     when(isIllegalAccess || !has) {
       raiseException(MExceptionCode.illegalInstruction)
     }
@@ -63,7 +63,7 @@ trait ZicsrExtension extends BaseCore with CommonDecode with ZicsrExtensionInsts
     // printf("PC: %x Inst:%x\n",now.pc,inst)
     when(CSRRW(inst)) {
       // t = CSRs[csr]; CSRs[csr] = x[rs1]; x[rd] = t
-      printf("Is CSRRW:%x\n",inst)
+      // printf("Is CSRRW:%x\n",inst)
       decodeI
       when(!wen(imm(11, 0))){
         when(rd =/= 0.U) {
@@ -75,7 +75,7 @@ trait ZicsrExtension extends BaseCore with CommonDecode with ZicsrExtensionInsts
     }
     when(CSRRS(inst)) {
       // t = CSRs[csr]; CSRs[csr] = t | x[rs1]; x[rd] = t
-      printf("Is CSRRS:%x\n",inst)
+      // printf("Is CSRRS:%x\n",inst)
       decodeI
       when(!wen(imm(11, 0), now.reg(rs1) === 0.U)){
         // imm_11_0, rs1 , funct3, rd             , opcode ), inst); 
@@ -90,7 +90,7 @@ trait ZicsrExtension extends BaseCore with CommonDecode with ZicsrExtensionInsts
     }
     when(CSRRC(inst)) {
       // t = CSRs[csr]; CSRs[csr] = t &~x[rs1]; x[rd] = t
-      printf("Is CSRRC:%x\n",inst)
+      // printf("Is CSRRC:%x\n",inst)
       decodeI
       when(!wen(imm(11, 0))){
         next.reg(rd) := zeroExt(csrRead(imm(11, 0)), XLEN)
@@ -102,7 +102,7 @@ trait ZicsrExtension extends BaseCore with CommonDecode with ZicsrExtensionInsts
     }
     when(CSRRWI(inst)) {
       // x[rd] = CSRs[csr]; CSRs[csr] = zimm
-      printf("Is CSRRWI:%x\n",inst)
+      // printf("Is CSRRWI:%x\n",inst)
       decodeI
       when(!wen(imm(11, 0))){
         when(rd =/= 0.U) {
@@ -113,7 +113,7 @@ trait ZicsrExtension extends BaseCore with CommonDecode with ZicsrExtensionInsts
     }
     when(CSRRSI(inst)) {
       // t = CSRs[csr]; CSRs[csr] = t | zimm; x[rd] = t
-      printf("Is CSRRSI:%x\n",inst)
+      // printf("Is CSRRSI:%x\n",inst)
       decodeI
       when(!wen(imm(11, 0), now.reg(rs1) === 0.U)){
         next.reg(rd) := zeroExt(csrRead(imm(11, 0)), XLEN)
@@ -125,7 +125,7 @@ trait ZicsrExtension extends BaseCore with CommonDecode with ZicsrExtensionInsts
     }
     when(CSRRCI(inst)) {
       // t = CSRs[csr]; CSRs[csr] = t &~zimm; x[rd] = t
-      printf("Is CSRRCI:%x\n",inst)
+      // printf("Is CSRRCI:%x\n",inst)
       decodeI
       when(!wen(imm(11, 0))){
         next.reg(rd) := zeroExt(csrRead(imm(11, 0)), XLEN)

src/main/scala/rvspeccore/core/spec/instset/csr/CSRSupport.scala

@@ -13,18 +13,18 @@ trait CSRSupport extends BaseCore with ExceptionSupport {
   // def ModeS     = 0x1.U // 01 Supervisor
   // def ModeR     = 0x2.U // 10 Reserved
   // def ModeM     = 0x3.U // 11 Machine
-  val lr = RegInit(Bool(), false.B)
-  val VAddrBits = if(XLEN == 32) 32 else 39
+  val lr        = RegInit(Bool(), false.B)
+  val VAddrBits = if (XLEN == 32) 32 else 39
   val retTarget = Wire(UInt(VAddrBits.W))
   retTarget := DontCare
   def csrRead(addr: UInt): UInt = {
     // Read the value of special registers
     // CSR addr require 12bit
     require(addr.getWidth == 12)
-    val has:    Bool = MuxLookup(addr, false.B)(now.csr.table.map { x => x.info.addr -> true.B })
-    val nowCSR: UInt = MuxLookup(addr, 0.U)(now.csr.table.map { x => x.info.addr -> x.signal })
-    val rmask:  UInt = MuxLookup(addr, 0.U)(now.csr.table.map { x => x.info.addr -> x.info.rmask })
-    printf("[Debug]CSR_READ:(Have:%d, nowCSR:%x, Addr: %x %x)\n",has,nowCSR,addr,next.reg(1))
+    val has: Bool    = MuxLookup(addr, false.B, now.csr.table.map { x => x.info.addr -> true.B })
+    val nowCSR: UInt = MuxLookup(addr, 0.U, now.csr.table.map { x => x.info.addr -> x.signal })
+    val rmask: UInt  = MuxLookup(addr, 0.U, now.csr.table.map { x => x.info.addr -> x.info.rmask })
+    // printf("[Debug]CSR_READ:(Have:%d, nowCSR:%x, Addr: %x %x)\n",has,nowCSR,addr,next.reg(1))
     val rData = WireInit(0.U(XLEN.W))
 
     def doCSRRead(MXLEN: Int): Unit = {
@@ -59,19 +59,19 @@ trait CSRSupport extends BaseCore with ExceptionSupport {
   def csrWrite(addr: UInt, data: UInt): Unit = {
     def UnwritableMask = 0.U(XLEN.W)
     require(addr.getWidth == 12)
-    val has: Bool = MuxLookup(addr, false.B)(now.csr.table.map { x => x.info.addr -> true.B })
+    val has: Bool = MuxLookup(addr, false.B, now.csr.table.map { x => x.info.addr -> true.B })
     when(has) {
       // require(mask.getWidth == XLEN)
       // common wirte
       val csrPairs = now.csr.table.zip(next.csr.table)
       csrPairs.foreach { case (CSRInfoSignal(info, nowCSR), CSRInfoSignal(_, nextCSR)) =>
         when(addr === info.addr) {
           // 地址是当前寄存器的地址
-          printf("[Debug]Find ADDR, %x %x\n", (info.wfn != null).B, (info.wmask != UnwritableMask).B)
+          // printf("[Debug]Find ADDR, %x %x\n", (info.wfn != null).B, (info.wmask != UnwritableMask).B)
           if (info.wfn != null && info.wmask != UnwritableMask) {
             // 且该寄存器可写 使用mask
             nextCSR := info.wfn((nowCSR & ~info.wmask) | (data & info.wmask))
-            printf("[Debug]CSR_Write:(Addr: %x, nowCSR: %x, nextCSR: %x)\n", addr, nowCSR, nextCSR)
+            // printf("[Debug]CSR_Write:(Addr: %x, nowCSR: %x, nextCSR: %x)\n", addr, nowCSR, nextCSR)
           } else {
             // TODO: might cause some exception?
 
@@ -80,11 +80,10 @@ trait CSRSupport extends BaseCore with ExceptionSupport {
       }
     }.otherwise {
       // all unimplemented CSR registers return 0
-      printf("[Error]CSR_Write:Not have this reg...\n")
+      // printf("[Error]CSR_Write:Not have this reg...\n")
       raiseException(MExceptionCode.illegalInstruction)
     }
 
-
     // special wirte
     // ...
   }
@@ -93,23 +92,23 @@ trait CSRSupport extends BaseCore with ExceptionSupport {
     when(priviledgeMode === ModeM) {
       val mstatusOld = WireInit(now.csr.mstatus.asTypeOf(new MstatusStruct))
       val mstatusNew = WireInit(now.csr.mstatus.asTypeOf(new MstatusStruct))
-      mstatusNew.mie   := mstatusOld.mpie
-      priviledgeMode   := mstatusOld.mpp
-      mstatusNew.mpie  := true.B
-      printf("MRET Mstatus: %x, Mode: %x\n", mstatusOld.asUInt, priviledgeMode)
-      if(config.CSRMisaExtList.exists(s => s == 'U')) {
+      mstatusNew.mie  := mstatusOld.mpie
+      priviledgeMode  := mstatusOld.mpp
+      mstatusNew.mpie := true.B
+      // printf("MRET Mstatus: %x, Mode: %x\n", mstatusOld.asUInt, priviledgeMode)
+      if (config.CSRMisaExtList.exists(s => s == 'U')) {
         mstatusNew.mpp := ModeU
       } else {
         mstatusNew.mpp := ModeM
       }
       next.csr.mstatus := mstatusNew.asUInt
-      lr := false.B
-      retTarget := next.csr.mepc(VAddrBits-1, 0)
-      printf("nextpc1:%x\n",now.csr.mepc)
+      lr               := false.B
+      retTarget        := next.csr.mepc(VAddrBits - 1, 0)
+      // printf("nextpc1:%x\n",now.csr.mepc)
       global_data.setpc := true.B
-      next.pc := now.csr.mepc
-      printf("nextpc2:%x\n",next.pc)
-    }.otherwise{
+      next.pc           := now.csr.mepc
+      // printf("nextpc2:%x\n",next.pc)
+    }.otherwise {
       raiseException(MExceptionCode.illegalInstruction)
     }
   }
@@ -121,25 +120,25 @@ trait CSRSupport extends BaseCore with ExceptionSupport {
     // return instruction, SRET. When TSR=1, attempts to execute SRET while executing in S-mode
     // will raise an illegal instruction exception. When TSR=0, this operation is permitted in S-mode.
     // TSR is read-only 0 when S-mode is not supported.
-    val illegalSret = priviledgeMode < ModeS
+    val illegalSret      = priviledgeMode < ModeS
     val illegalSModeSret = priviledgeMode === ModeS && mstatusOld.tsr.asBool
-    when(illegalSret || illegalSModeSret){
+    when(illegalSret || illegalSModeSret) {
       raiseException(MExceptionCode.illegalInstruction)
-    }.otherwise{
+    }.otherwise {
       // FIXME: is mstatus not sstatus ?
       mstatusNew.sie   := mstatusOld.spie
       priviledgeMode   := Cat(0.U(1.W), mstatusOld.spp)
       mstatusNew.spie  := true.B // 正确的
       mstatusNew.spp   := ModeU
-      mstatusNew.mprv  := 0x0.U // Volume II P21 " If xPP != M, xRET also sets MPRV = 0 "
+      mstatusNew.mprv  := 0x0.U  // Volume II P21 " If xPP != M, xRET also sets MPRV = 0 "
       next.csr.mstatus := mstatusNew.asUInt
-      lr := false.B
-      retTarget := next.csr.sepc(VAddrBits-1, 0)
-      printf("nextpc1:%x\n",now.csr.sepc)
+      lr               := false.B
+      retTarget        := next.csr.sepc(VAddrBits - 1, 0)
+      // printf("nextpc1:%x\n",now.csr.sepc)
       global_data.setpc := true.B
-      next.pc := now.csr.sepc
-      printf("nextpc2:%x\n",next.pc)
-      printf("next mstatus:%x\n", next.csr.mstatus)
+      next.pc           := now.csr.sepc
+      // printf("nextpc2:%x\n",next.pc)
+      // printf("next mstatus:%x\n", next.csr.mstatus)
     }
   }
 }