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feat: remove tlb temporary
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@SeddonShen
SeddonShen committed Aug 16, 2024
1 parent 33fde1e commit 85674a0
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Showing 4 changed files with 574 additions and 571 deletions.
150 changes: 75 additions & 75 deletions src/main/scala/rvspeccore/checker/Checker.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,8 @@ import chisel3.util._

import rvspeccore.core._
import rvspeccore.core.spec.instset.csr.EventSig
import rvspeccore.core.tool.TLBMemInfo
import rvspeccore.core.tool.TLBSig
//import rvspeccore.core.tool.TLBMemInfo
//import rvspeccore.core.tool.TLBSig

abstract class Checker()(implicit config: RVConfig) extends Module {
implicit val XLEN: Int = config.XLEN
Expand Down Expand Up @@ -61,8 +61,8 @@ class CheckerWithResult(checkMem: Boolean = true, enableReg: Boolean = false)(im
val result = Input(State())
val mem = if (checkMem) Some(Input(new MemIO)) else None
val event = Input(new EventSig())
val dtlbmem = if (checkMem) Some(Input(new TLBSig)) else None
val itlbmem = if (checkMem) Some(Input(new TLBSig)) else None
// val dtlbmem = if (checkMem) Some(Input(new TLBSig)) else None
// val itlbmem = if (checkMem) Some(Input(new TLBSig)) else None
})
// TODO: io.result has .internal states now, consider use it or not

Expand All @@ -81,80 +81,80 @@ class CheckerWithResult(checkMem: Boolean = true, enableReg: Boolean = false)(im
specCore.io.inst := io.instCommit.inst

// initial another io.mem.get.Anotherread
for (i <- 0 until 6) {
specCore.io.tlb.Anotherread(i).data := DontCare
}
// for (i <- 0 until 6) {
// specCore.io.tlb.Anotherread(i).data := DontCare
// }

// assertions

if (checkMem) {
// printf("[specCore] Valid:%x PC: %x Inst: %x\n", specCore.io.valid, specCore.io.now.pc, specCore.io.inst)
// specCore.io.mem.read.data := { if (checkMem) io.mem.get.read.data else DontCare }
val TLBLoadQueue = Seq.fill(3)(Module(new QueueModuleTLB()))
val tlb_load_push = Wire(new StoreOrLoadInfoTLB)
// initial the queue
for (i <- 0 until 3) {
TLBLoadQueue(i).io.out.ready := false.B
TLBLoadQueue(i).io.in.valid := false.B
TLBLoadQueue(i).io.in.bits := 0.U.asTypeOf(new StoreOrLoadInfoTLB)
}
when(io.dtlbmem.get.read.valid) {
tlb_load_push.addr := io.dtlbmem.get.read.addr
tlb_load_push.data := io.dtlbmem.get.read.data
tlb_load_push.level := io.dtlbmem.get.read.level
assert(RegNext(TLBLoadQueue(0).io.in.valid, false.B) === false.B)
assert(RegNext(TLBLoadQueue(0).io.in.bits.addr, 0.U) === 0.U)
assert(RegNext(TLBLoadQueue(0).io.in.bits.data, 0.U) === 0.U)
assert(RegNext(TLBLoadQueue(0).io.in.bits.level, 0.U) === 0.U)
assert(RegNext(TLBLoadQueue(1).io.in.valid, false.B) === false.B)
assert(RegNext(TLBLoadQueue(1).io.in.bits.addr, 0.U) === 0.U)
assert(RegNext(TLBLoadQueue(1).io.in.bits.data, 0.U) === 0.U)
assert(RegNext(TLBLoadQueue(1).io.in.bits.level, 0.U) === 0.U)
assert(RegNext(TLBLoadQueue(2).io.in.valid, false.B) === false.B)
assert(RegNext(TLBLoadQueue(2).io.in.bits.addr, 0.U) === 0.U)
assert(RegNext(TLBLoadQueue(2).io.in.bits.data, 0.U) === 0.U)
assert(RegNext(TLBLoadQueue(2).io.in.bits.level, 0.U) === 0.U)

for (i <- 0 until 3) {
TLBLoadQueue(i).io.in.valid := false.B
TLBLoadQueue(i).io.in.bits := 0.U.asTypeOf(new StoreOrLoadInfoTLB)
}
switch(io.dtlbmem.get.read.level) {
is(0.U) {
TLBLoadQueue(0).io.in.valid := true.B
TLBLoadQueue(0).io.in.bits := tlb_load_push
}
is(1.U) {
TLBLoadQueue(1).io.in.valid := true.B
TLBLoadQueue(1).io.in.bits := tlb_load_push
}
is(2.U) {
TLBLoadQueue(2).io.in.valid := true.B
TLBLoadQueue(2).io.in.bits := tlb_load_push
}
is(3.U) {}
}
}.otherwise {
for (i <- 0 until 3) {
TLBLoadQueue(i).io.in.valid := false.B
tlb_load_push := 0.U.asTypeOf(new StoreOrLoadInfoTLB)
TLBLoadQueue(i).io.in.bits := tlb_load_push
}
}
for (i <- 0 until 3) {
when(specCore.io.tlb.Anotherread(i).valid) {
TLBLoadQueue(2 - i).io.out.ready := true.B
// printf("Load out Queue.... valid: %x %x %x %x\n", LoadQueue.io.out.valid, LoadQueue.io.out.bits.addr, LoadQueue.io.out.bits.data, LoadQueue.io.out.bits.memWidth)
specCore.io.tlb.Anotherread(i).data := { if (checkMem) TLBLoadQueue(2 - i).io.out.bits.data else DontCare }
// TODO: 第Level 1 assert is inconsistent nutshell and the condition need to modify.
// assert(TLBLoadQueue(i).io.out.bits.addr === specCore.io.mem.read.addr)
}.otherwise {
TLBLoadQueue(2 - i).io.out.ready := false.B
}
when(regDelay(specCore.io.tlb.Anotherread(i).valid)) {
assert(regDelay(TLBLoadQueue(2 - i).io.out.bits.addr) === regDelay(specCore.io.tlb.Anotherread(i).addr))
}
}
// val TLBLoadQueue = Seq.fill(3)(Module(new QueueModuleTLB()))
// val tlb_load_push = Wire(new StoreOrLoadInfoTLB)
// // initial the queue
// for (i <- 0 until 3) {
// TLBLoadQueue(i).io.out.ready := false.B
// TLBLoadQueue(i).io.in.valid := false.B
// TLBLoadQueue(i).io.in.bits := 0.U.asTypeOf(new StoreOrLoadInfoTLB)
// }
// when(io.dtlbmem.get.read.valid) {
// tlb_load_push.addr := io.dtlbmem.get.read.addr
// tlb_load_push.data := io.dtlbmem.get.read.data
// tlb_load_push.level := io.dtlbmem.get.read.level
// assert(RegNext(TLBLoadQueue(0).io.in.valid, false.B) === false.B)
// assert(RegNext(TLBLoadQueue(0).io.in.bits.addr, 0.U) === 0.U)
// assert(RegNext(TLBLoadQueue(0).io.in.bits.data, 0.U) === 0.U)
// assert(RegNext(TLBLoadQueue(0).io.in.bits.level, 0.U) === 0.U)
// assert(RegNext(TLBLoadQueue(1).io.in.valid, false.B) === false.B)
// assert(RegNext(TLBLoadQueue(1).io.in.bits.addr, 0.U) === 0.U)
// assert(RegNext(TLBLoadQueue(1).io.in.bits.data, 0.U) === 0.U)
// assert(RegNext(TLBLoadQueue(1).io.in.bits.level, 0.U) === 0.U)
// assert(RegNext(TLBLoadQueue(2).io.in.valid, false.B) === false.B)
// assert(RegNext(TLBLoadQueue(2).io.in.bits.addr, 0.U) === 0.U)
// assert(RegNext(TLBLoadQueue(2).io.in.bits.data, 0.U) === 0.U)
// assert(RegNext(TLBLoadQueue(2).io.in.bits.level, 0.U) === 0.U)
//
// for (i <- 0 until 3) {
// TLBLoadQueue(i).io.in.valid := false.B
// TLBLoadQueue(i).io.in.bits := 0.U.asTypeOf(new StoreOrLoadInfoTLB)
// }
// switch(io.dtlbmem.get.read.level) {
// is(0.U) {
// TLBLoadQueue(0).io.in.valid := true.B
// TLBLoadQueue(0).io.in.bits := tlb_load_push
// }
// is(1.U) {
// TLBLoadQueue(1).io.in.valid := true.B
// TLBLoadQueue(1).io.in.bits := tlb_load_push
// }
// is(2.U) {
// TLBLoadQueue(2).io.in.valid := true.B
// TLBLoadQueue(2).io.in.bits := tlb_load_push
// }
// is(3.U) {}
// }
// }.otherwise {
// for (i <- 0 until 3) {
// TLBLoadQueue(i).io.in.valid := false.B
// tlb_load_push := 0.U.asTypeOf(new StoreOrLoadInfoTLB)
// TLBLoadQueue(i).io.in.bits := tlb_load_push
// }
// }
// for (i <- 0 until 3) {
// when(specCore.io.tlb.Anotherread(i).valid) {
// TLBLoadQueue(2 - i).io.out.ready := true.B
// // printf("Load out Queue.... valid: %x %x %x %x\n", LoadQueue.io.out.valid, LoadQueue.io.out.bits.addr, LoadQueue.io.out.bits.data, LoadQueue.io.out.bits.memWidth)
// specCore.io.tlb.Anotherread(i).data := { if (checkMem) TLBLoadQueue(2 - i).io.out.bits.data else DontCare }
// // TODO: 第Level 1 assert is inconsistent nutshell and the condition need to modify.
// // assert(TLBLoadQueue(i).io.out.bits.addr === specCore.io.mem.read.addr)
// }.otherwise {
// TLBLoadQueue(2 - i).io.out.ready := false.B
// }
// when(regDelay(specCore.io.tlb.Anotherread(i).valid)) {
// assert(regDelay(TLBLoadQueue(2 - i).io.out.bits.addr) === regDelay(specCore.io.tlb.Anotherread(i).addr))
// }
// }
val LoadQueue = Module(new QueueModule)
val StoreQueue = Module(new QueueModule)
LoadQueue.io.out.ready := false.B
Expand Down Expand Up @@ -275,9 +275,9 @@ class CheckerWithWB(checkMem: Boolean = true)(implicit config: RVConfig) extends
specCore.io.mem.read.data := { if (checkMem) io.mem.get.read.data else DontCare }

// initial another io.mem.get.Anotherread
for (i <- 0 until 6) {
specCore.io.tlb.Anotherread(i).data := DontCare
}
// for (i <- 0 until 6) {
// specCore.io.tlb.Anotherread(i).data := DontCare
// }
val specCoreWBValid = WireInit(false.B)
val specCoreWBDest = WireInit(0.U(5.W))
for (i <- 0 until 32) {
Expand Down
64 changes: 32 additions & 32 deletions src/main/scala/rvspeccore/checker/ConnectHelper.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,8 +7,8 @@ import chisel3.util.experimental.BoringUtils
import rvspeccore.core.RVConfig
import rvspeccore.core.spec.instset.csr.CSR
import rvspeccore.core.spec.instset.csr.EventSig
import rvspeccore.core.tool.TLBMemInfo
import rvspeccore.core.tool.TLBSig
//import rvspeccore.core.tool.TLBMemInfo
//import rvspeccore.core.tool.TLBSig
abstract class ConnectHelper {}

/** Connect RegFile to io.result.reg by BoringUtils
Expand All @@ -33,28 +33,28 @@ object ConnectCheckerResult extends ConnectHelper {
val read = new MemOneSig
val write = new MemOneSig
}
def makeTLBSource(isDTLB: Boolean)(implicit XLEN: Int): TLBSig = {
val tlbmem = Wire(new TLBSig())
tlbmem.read.valid := false.B
tlbmem.read.addr := 0.U
tlbmem.read.data := 0.U
tlbmem.read.memWidth := 0.U
tlbmem.read.access := false.B
tlbmem.read.level := 0.U
tlbmem.write.valid := false.B
tlbmem.write.addr := 0.U
tlbmem.write.data := 0.U
tlbmem.write.memWidth := 0.U
tlbmem.write.access := false.B
tlbmem.write.level := 0.U

if (isDTLB) {
BoringUtils.addSource(tlbmem, uniqueIdDTLB)
} else {
BoringUtils.addSource(tlbmem, uniqueIdITLB)
}
tlbmem
}
// def makeTLBSource(isDTLB: Boolean)(implicit XLEN: Int): TLBSig = {
// val tlbmem = Wire(new TLBSig())
// tlbmem.read.valid := false.B
// tlbmem.read.addr := 0.U
// tlbmem.read.data := 0.U
// tlbmem.read.memWidth := 0.U
// tlbmem.read.access := false.B
// tlbmem.read.level := 0.U
// tlbmem.write.valid := false.B
// tlbmem.write.addr := 0.U
// tlbmem.write.data := 0.U
// tlbmem.write.memWidth := 0.U
// tlbmem.write.access := false.B
// tlbmem.write.level := 0.U
//
// if (isDTLB) {
// BoringUtils.addSource(tlbmem, uniqueIdDTLB)
// } else {
// BoringUtils.addSource(tlbmem, uniqueIdITLB)
// }
// tlbmem
// }
def makeMemSource()(implicit XLEN: Int) = {
val mem = Wire(new MemSig)

Expand Down Expand Up @@ -105,16 +105,16 @@ object ConnectCheckerResult extends ConnectHelper {

if (checker.io.mem != None) {
val mem = Wire(new MemSig)
val dtlbmem = Wire(new TLBSig)
val itlbmem = Wire(new TLBSig)
// val dtlbmem = Wire(new TLBSig)
// val itlbmem = Wire(new TLBSig)
mem := DontCare
dtlbmem := DontCare
itlbmem := DontCare
// dtlbmem := DontCare
// itlbmem := DontCare
BoringUtils.addSink(mem, uniqueIdMem)
BoringUtils.addSink(dtlbmem, uniqueIdDTLB)
BoringUtils.addSink(itlbmem, uniqueIdITLB)
checker.io.dtlbmem.get := dtlbmem
checker.io.itlbmem.get := itlbmem
// BoringUtils.addSink(dtlbmem, uniqueIdDTLB)
// BoringUtils.addSink(itlbmem, uniqueIdITLB)
// checker.io.dtlbmem.get := dtlbmem
// checker.io.itlbmem.get := itlbmem
checker.io.mem.get := regNextDelay(mem, memDelay)
// expose the signal below
// assert(RegNext(checker.io.dtlbmem.get.read.valid, false.B) === false.B)
Expand Down
31 changes: 16 additions & 15 deletions src/main/scala/rvspeccore/core/RiscvCore.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ abstract class BaseCore()(implicit config: RVConfig) extends Module {
val inst = Input(UInt(32.W))
val valid = Input(Bool())
val mem = new MemIO
val tlb = new TLBIO
// val tlb = new TLBIO
// Exposed processor status
val now = Output(State())
val next = Output(State())
Expand All @@ -27,7 +27,7 @@ abstract class BaseCore()(implicit config: RVConfig) extends Module {
val now = RegInit(State.wireInit())
val next = Wire(State())
val mem = Wire(new MemIO)
val tlb = Wire(new TLBIO)
// val tlb = Wire(new TLBIO)
// Global Data
val global_data = Wire(new GlobalData) // TODO: GlobalData only has setpc? event, iFetchpc?
val event = Wire(new EventSig)
Expand Down Expand Up @@ -55,10 +55,10 @@ class MemIO()(implicit XLEN: Int) extends Bundle {
val write = new WriteMemIO
}

class TLBIO()(implicit XLEN: Int) extends Bundle {
val Anotherread = Vec(3 + 3, new ReadMemIO())
val Anotherwrite = Vec(3, new WriteMemIO())
}
//class TLBIO()(implicit XLEN: Int) extends Bundle {
// val Anotherread = Vec(3 + 3, new ReadMemIO())
// val Anotherwrite = Vec(3, new WriteMemIO())
//}

class Internal() extends Bundle {
val privilegeMode = UInt(2.W)
Expand Down Expand Up @@ -105,21 +105,22 @@ class RiscvCore()(implicit config: RVConfig) extends BaseCore with RVInstSet {
// dont read or write mem
// if there no LOAD/STORE below
mem := 0.U.asTypeOf(new MemIO)
tlb := 0.U.asTypeOf(new TLBIO)
// tlb := 0.U.asTypeOf(new TLBIO)

// ID & EXE
when(io.valid) {
// CSR
// TODO: merge into a function?
next.csr.cycle := now.csr.cycle + 1.U
exceptionSupportInit()
val (resultStatus, resultPC) = if (XLEN == 32) (true.B, now.pc) else iFetchTrans(now.pc)
when(resultStatus) {
inst := io.inst
}.otherwise {
inst := 0.U(XLEN.W) // With a NOP instruction
}
iFetchpc := resultPC
// val (resultStatus, resultPC) = if (XLEN == 32) (true.B, now.pc) else iFetchTrans(now.pc)
inst := io.inst
// when(resultStatus) {
// inst := io.inst
// }.otherwise {
// inst := 0.U(XLEN.W) // With a NOP instruction
// }
iFetchpc := now.pc

// Decode and Excute
config.XLEN match {
Expand Down Expand Up @@ -157,7 +158,7 @@ class RiscvCore()(implicit config: RVConfig) extends BaseCore with RVInstSet {

// mem port
io.mem <> mem
io.tlb <> tlb
// io.tlb <> tlb

// update
now := next
Expand Down
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