feat: Add SocTop and modify the AXI4RAM

src/main/scala/rvspeccore/core/RiscvCore.scala

@@ -71,7 +71,8 @@ class RiscvCore()(implicit config: RVConfig) extends BaseCore with RVInstSet {
   // ID & EXE
   when(io.valid) {
     inst := io.inst
-
+    // print inst and pc
+    printf("inst: %x, pc: %x\n", inst, now.pc)
     // Decode and Excute
     config match {
       case RV32Config(_) => {

src/main/scala/rvspeccore/core/SocTop.scala

@@ -0,0 +1,47 @@
+package rvspeccore.core
+import chisel3._
+import chisel3.util._
+import rvspeccore.bus.axi4._
+import rvspeccore.device.AXI4RAM
+
+class SoCTop(genCore: => RiscvCore)(implicit config: RVConfig) extends Module {
+    val io = IO(new Bundle {
+        val mem = new AXI4
+    })
+    val core = Module(genCore)
+    val pc   = core.io.now.pc - "h8000_0000".U
+    printf("[SoCTop] pc = %d\n", pc)
+    // val inst = Wire(UInt(32.W))
+
+    core.io.valid := !reset.asBool
+    core.io.mem.read.data := 0.U
+    core.io.inst := "h00b00193".U
+    io.mem.ar.bits.addr  := 0.U
+    io.mem.ar.valid      := 0.U
+    io.mem.ar.bits.size  := 0.U
+    io.mem.ar.bits.len   := 0.U
+    io.mem.r.ready       := 0.U
+    io.mem.aw.valid      := 0.U
+    io.mem.aw.bits.addr  := "h0000_0000".U
+    io.mem.aw.bits.size  := 4.U
+    io.mem.aw.bits.len   := 1.U
+    io.mem.w.bits.data   := 0.U
+    io.mem.w.bits.strb   := 0.U
+    io.mem.w.bits.last   := 0.U
+    io.mem.w.valid       := 0.U
+    io.mem.aw.bits.user  := 0.U
+    io.mem.aw.bits.burst := 0.U
+    io.mem.aw.bits.cache := 0.U
+    io.mem.aw.bits.prot  := 0.U
+    io.mem.aw.bits.lock  := 0.U
+    io.mem.aw.bits.qos   := 0.U
+    io.mem.aw.bits.id    := 0.U
+    io.mem.ar.bits.prot  := 0.U
+    io.mem.ar.bits.burst := 0.U
+    io.mem.ar.bits.cache := 0.U
+    io.mem.ar.bits.user  := 0.U
+    io.mem.ar.bits.qos   := 0.U
+    io.mem.ar.bits.lock  := 0.U
+    io.mem.ar.bits.id    := 0.U
+    io.mem.b.ready       := 0.U
+}

src/main/scala/rvspeccore/device/AXI4RAM.scala

@@ -37,7 +37,7 @@ class RAMHelper(memByte: Int) extends BlackBox {
 }
 
 class AXI4RAM[T <: AXI4Lite](_type: T = new AXI4, memByte: Int,
-  useBlackBox: Boolean = false) extends AXI4SlaveModule(_type) {
+  useBlackBox: Boolean = false, memFile: String) extends AXI4SlaveModule(_type) {
 
   val offsetBits = log2Up(memByte)
   val offsetMask = (1 << offsetBits) - 1
@@ -59,17 +59,23 @@ class AXI4RAM[T <: AXI4Lite](_type: T = new AXI4, memByte: Int,
     mem.io.en := true.B
     mem.io.rdata
   } else {
-    val mem = Mem(memByte / 8, Vec(8, UInt(8.W)))
+    val mem = Mem(memByte, UInt(64.W))
 
-    val wdata = VecInit.tabulate(8) { i => in.w.bits.data(8*(i+1)-1, 8*i) }
-    // print in.w.fire and inRange(wIdx)
-    printf("[AXI4RAM] in.w.ready = %d, in.w.valid = %d, inRange(wIdx) = %d\n", in.w.ready, in.w.valid, inRange(wIdx))
-    when (wen) { 
-      // print widx and wdata
-      printf("[AXI4RAM------] wIdx = %d, wdata = %d\n", wIdx, in.w.bits.data)
-      mem.write(wIdx, wdata, in.w.bits.strb.asBools) 
+    if (memFile != ""){
+      loadMemoryFromFile(mem, memFile)
     }
-    Cat(mem.read(rIdx).reverse)
+
+    // Firstly enable to read
+    // FIXME: Can not write anymore
+    // val wdata = VecInit.tabulate(8) { i => in.w.bits.data(8*(i+1)-1, 8*i) }
+    // // print in.w.fire and inRange(wIdx)
+    // printf("[AXI4RAM] in.w.ready = %d, in.w.valid = %d, inRange(wIdx) = %d\n", in.w.ready, in.w.valid, inRange(wIdx))
+    // when (wen) { 
+    //   // print widx and wdata
+    //   printf("[AXI4RAM------] wIdx = %d, wdata = %d\n", wIdx, in.w.bits.data)
+    //   // mem.write(wIdx, wdata, in.w.bits.strb.asBools) 
+    // }
+    Cat(mem.read(rIdx))
   }
   when(ren) {
     printf("[AXI4RAM] rIdx = %d, rdata = %d\n", rIdx, rdata)

src/test/scala/rvspeccore/core/SocTopSpec.scala

@@ -0,0 +1,29 @@
+// See README.md for license details.
+
+package rvspeccore.core
+
+import chisel3._
+import chiseltest._
+import org.scalatest.freespec.AnyFreeSpec
+import chisel3.experimental.BundleLiterals._
+import rvspeccore.device.AXI4RAM
+import rvspeccore.bus.axi4._
+
+class SoC() extends Module {
+    // val Spec = Module(new SpecCore)
+    implicit val config = RV32Config("MC")
+
+    val mem = Module(new AXI4RAM(new AXI4, 1024 * 1024 * 4, false, "./testcase/riscv-tests-hex/rv32ui/rv32ui-add.hex"))
+    val memdelay = Module(new AXI4Delayer(0))
+    val core = Module(new SoCTop(new RiscvCore))
+    memdelay.io.in <> core.io.mem
+    mem.io.in <> memdelay.io.out
+}
+
+class SocTopSpec extends AnyFreeSpec with ChiselScalatestTester {
+  "SocTopSpec pass" in {
+    test(new SoC()) { dut =>
+      dut.clock.step(20)
+    }
+  }
+}