feat: full 32bit version for rv-mini and NutShell(patch)

iscas-tis · Aug 26, 2024 · 2650dde · 2650dde
1 parent 8e68f41
commit 2650dde
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Showing 2 changed files with 10 additions and 3 deletions.
diff --git a/src/main/scala/rvspeccore/checker/ArbitraryGenerater.scala b/src/main/scala/rvspeccore/checker/ArbitraryGenerater.scala
@@ -14,8 +14,10 @@ object ArbitraryRegFile {
   }
   def init(implicit XLEN: Int): Vec[UInt] = {
     val rf = Wire(Vec(32, UInt(XLEN.W)))
-    rf.map(_ := DontCare)
-    rf(0) := 0.U
+    // rf.map(_ := DontCare)
+    rf.map(_ := 0.U)
+    rf(1) := DontCare
+    rf(2) := DontCare
     BoringUtils.addSource(rf, uniqueIdArbitraryRegFile)
     rf
   }

diff --git a/src/main/scala/rvspeccore/checker/Checker.scala b/src/main/scala/rvspeccore/checker/Checker.scala
@@ -55,7 +55,12 @@ class CheckerWithResult(checkMem: Boolean = true, enableReg: Boolean = false)(im
         assert(io.mem.get.read.addr === specCore.io.mem.read.addr)
         assert(io.mem.get.read.memWidth === specCore.io.mem.read.memWidth)
       }
-      assert(io.mem.get.write.valid === specCore.io.mem.write.valid)  
+      assert(io.mem.get.write.valid === specCore.io.mem.write.valid)
+      when(io.mem.get.write.valid || specCore.io.mem.write.valid){
+        assert(io.mem.get.write.addr === specCore.io.mem.write.addr)
+        assert(io.mem.get.write.data === specCore.io.mem.write.data)
+        assert(io.mem.get.write.memWidth === specCore.io.mem.write.memWidth)
+      }
       specCore.io.mem.read.data := io.mem.get.read.data
   } else {
     specCore.io.mem.read.data := DontCare