Skip to content

Commit

Permalink
feat: add dmem port, but need add crossbar
Browse files Browse the repository at this point in the history
  • Loading branch information
@SeddonShen
SeddonShen committed Oct 22, 2023
1 parent 38265f9 commit 0ad5685
Show file tree
Hide file tree
Showing 2 changed files with 97 additions and 52 deletions.
124 changes: 78 additions & 46 deletions src/main/scala/rvspeccore/core/SocTop.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,69 +6,101 @@ import rvspeccore.device.AXI4RAM

class SoCTop(genCore: => RiscvCore)(implicit config: RVConfig) extends Module {
val io = IO(new Bundle {
val mem = new AXI4
val imem = new AXI4
val dmem = new AXI4
})
val core = Module(genCore)
val s_idle :: s_reading :: s_readend :: Nil = Enum(3)
val read_state = RegInit(s_idle)
val s_i_idle :: s_i_reading :: s_i_readend :: Nil = Enum(3)
val read_state = RegInit(s_i_idle)
val pc = core.io.now.pc - "h8000_0000".U
// printf("[SoCTop] pc = %d Bool = %d State = %d\n", pc, !reset.asBool, read_state)
// val inst = Wire(UInt(32.W))
core.io.valid := false.B
core.io.mem.read.data := 0.U
core.io.inst := 0.U
// core.io.inst := "h00b00193".U
io.mem.ar.bits.addr := 0.U
io.mem.ar.valid := 0.U
io.mem.ar.bits.size := 0.U
io.mem.ar.bits.len := 0.U
io.mem.r.ready := 0.U
io.mem.aw.valid := 0.U
io.mem.aw.bits.addr := "h0000_0000".U
io.mem.aw.bits.size := 0.U
io.mem.aw.bits.len := 0.U
io.mem.w.bits.data := 0.U
io.mem.w.bits.strb := 0.U
io.mem.w.bits.last := 0.U
io.mem.w.valid := 0.U
io.mem.aw.bits.user := 0.U
io.mem.aw.bits.burst := 0.U
io.mem.aw.bits.cache := 0.U
io.mem.aw.bits.prot := 0.U
io.mem.aw.bits.lock := 0.U
io.mem.aw.bits.qos := 0.U
io.mem.aw.bits.id := 0.U
io.mem.ar.bits.prot := 0.U
io.mem.ar.bits.burst := 0.U
io.mem.ar.bits.cache := 0.U
io.mem.ar.bits.user := 0.U
io.mem.ar.bits.qos := 0.U
io.mem.ar.bits.lock := 0.U
io.mem.ar.bits.id := 0.U
io.mem.b.ready := 0.U
io.imem.ar.bits.addr := 0.U
io.imem.ar.valid := 0.U
io.imem.ar.bits.size := 0.U
io.imem.ar.bits.len := 0.U
io.imem.r.ready := 0.U
io.imem.aw.valid := 0.U
io.imem.aw.bits.addr := "h0000_0000".U
io.imem.aw.bits.size := 0.U
io.imem.aw.bits.len := 0.U
io.imem.w.bits.data := 0.U
io.imem.w.bits.strb := 0.U
io.imem.w.bits.last := 0.U
io.imem.w.valid := 0.U
io.imem.aw.bits.user := 0.U
io.imem.aw.bits.burst := 0.U
io.imem.aw.bits.cache := 0.U
io.imem.aw.bits.prot := 0.U
io.imem.aw.bits.lock := 0.U
io.imem.aw.bits.qos := 0.U
io.imem.aw.bits.id := 0.U
io.imem.ar.bits.prot := 0.U
io.imem.ar.bits.burst := 0.U
io.imem.ar.bits.cache := 0.U
io.imem.ar.bits.user := 0.U
io.imem.ar.bits.qos := 0.U
io.imem.ar.bits.lock := 0.U
io.imem.ar.bits.id := 0.U
io.imem.b.ready := 0.U

// dmem
io.dmem.ar.bits.addr := 0.U
io.dmem.ar.valid := 0.U
io.dmem.ar.bits.size := 0.U
io.dmem.ar.bits.len := 0.U
io.dmem.r.ready := 0.U
io.dmem.aw.valid := 0.U
io.dmem.aw.bits.addr := "h0000_0000".U
io.dmem.aw.bits.size := 0.U
io.dmem.aw.bits.len := 0.U
io.dmem.w.bits.data := 0.U
io.dmem.w.bits.strb := 0.U
io.dmem.w.bits.last := 0.U
io.dmem.w.valid := 0.U
io.dmem.aw.bits.user := 0.U
io.dmem.aw.bits.burst := 0.U
io.dmem.aw.bits.cache := 0.U
io.dmem.aw.bits.prot := 0.U
io.dmem.aw.bits.lock := 0.U
io.dmem.aw.bits.qos := 0.U
io.dmem.aw.bits.id := 0.U
io.dmem.ar.bits.prot := 0.U
io.dmem.ar.bits.burst := 0.U
io.dmem.ar.bits.cache := 0.U
io.dmem.ar.bits.user := 0.U
io.dmem.ar.bits.qos := 0.U
io.dmem.ar.bits.lock := 0.U
io.dmem.ar.bits.id := 0.U
io.dmem.b.ready := 0.U

// 读-状态机
switch(read_state) {
is(s_idle) {
is(s_i_idle) {
when(!reset.asBool){
read_state := s_reading
read_state := s_i_reading
}
}
is(s_reading) {
io.mem.ar.bits.id := 0.U // For inst mem
io.mem.ar.bits.addr := pc
io.mem.ar.bits.size := 4.U
io.mem.ar.bits.burst := 1.U
io.mem.ar.valid := 1.U
when(io.mem.ar.ready){
read_state := s_readend
is(s_i_reading) {
io.imem.ar.bits.id := 0.U // For inst mem
io.imem.ar.bits.addr := pc
io.imem.ar.bits.size := 4.U
io.imem.ar.bits.burst := 1.U
io.imem.ar.valid := 1.U
when(io.imem.ar.ready){
read_state := s_i_readend
}
}
is(s_readend) {
io.mem.r.ready := 1.U
when(io.mem.r.fire){
is(s_i_readend) {
io.imem.r.ready := 1.U
when(io.imem.r.fire){
core.io.valid := true.B
core.io.inst := io.mem.r.bits.data
read_state := s_idle
core.io.inst := io.imem.r.bits.data
read_state := s_i_idle
}
}
}
Expand Down
25 changes: 19 additions & 6 deletions src/test/scala/rvspeccore/core/SocTopSpec.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,18 +12,31 @@ class SoC() extends Module {
// val Spec = Module(new SpecCore)
implicit val config = RV32Config("MC")

val mem = Module(new AXI4RAM(new AXI4, 1024 * 1024 * 4, false, "./testcase/riscv-tests-hex/rv32ui/rv32ui-add.hex"))
val memdelay = Module(new AXI4Delayer(0))
// because we not have axi crossbar now
val imem = Module(new AXI4RAM(new AXI4, 1024 * 1024 * 4, false, "./testcase/riscv-tests-hex/rv32ui/rv32ui-add.hex"))
val dmem = Module(new AXI4RAM(new AXI4, 1024 * 1024 * 4, false, "./testcase/riscv-tests-hex/rv32ui/rv32ui-add.hex"))
val i_memdelay = Module(new AXI4Delayer(0))
val d_memdelay = Module(new AXI4Delayer(0))
val soc = Module(new SoCTop(new RiscvCore))
memdelay.io.in <> soc.io.mem
mem.io.in <> memdelay.io.out
i_memdelay.io.in <> soc.io.imem
imem.io.in <> i_memdelay.io.out

d_memdelay.io.in <> soc.io.dmem
dmem.io.in <> d_memdelay.io.out
}

class SocTopSpec extends AnyFreeSpec with ChiselScalatestTester {
"SocTopSpec pass" in {
test(new SoC()) { dut =>
dut.clock.setTimeout(2000)
dut.clock.step(1990)
dut.clock.setTimeout(300)
dut.clock.step(200)
}
}
}
class GenerateSocVerilog extends AnyFreeSpec with ChiselScalatestTester {
"GenerateSocVerilog pass" in {
implicit val config = RV32Config("MC")
(new chisel3.stage.ChiselStage)
.emitVerilog(new SoCTop(new RiscvCore), Array("--target-dir", "test_run_dir/GenerateSocVerilog"))
}
}

0 comments on commit 0ad5685

Please sign in to comment.