Debug on CI

Signed-off-by: erman-gurses <erman@nod-labs.com>
iree-org · Feb 8, 2025 · 9bce23a · 9bce23a
1 parent ab768c6
commit 9bce23a
Showing 1 changed file with 34 additions and 32 deletions.
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/Verifiers.cpp b/compiler/src/iree/compiler/Codegen/LLVMGPU/Verifiers.cpp
@@ -80,51 +80,53 @@ verifyGPUMatmulPipeline(Operation *op,
 
   if (pipeline != CodeGenPipeline::LLVMGPUMatmulTensorCore &&
       pipeline != CodeGenPipeline::LLVMGPUMatmulTensorCoreMmaSync &&
-      pipeline != CodeGenPipeline::LLVMGPUTileAndFuse &&
       pipeline != CodeGenPipeline::LLVMGPUVectorDistribute) {
     return success();
   }
 
-  uint32_t reduction = static_cast<uint32_t>(IREE::GPU::TilingLevel::Reduction);
-  uint numLoops = llvm::cast<linalg::LinalgOp>(op).getNumLoops();
+  // Only verify batched and unbatched matmul.
+  if (!isa<linalg::MatmulOp, linalg::BatchMatmulOp>(op)) {
+    return success();
+  }
 
-  SmallVector<int64_t> reductionTileSizes =
-      gpuLoweringConfig.getStaticTilingLevelSizes(reduction, op);
-  size_t size = reductionTileSizes.size();
+  uint32_t reduction = static_cast<uint32_t>(IREE::GPU::TilingLevel::Reduction);
+  reduction++;
+  uint numLoops = llvm::cast<linalg::MatmulOp>(op).getNumLoops();
+  numLoops++;
+  // size_t size = 0;
+  // if (gpuLoweringConfig.hasTilingLevel(reduction)) {
+  //   SmallVector<int64_t> reductionTileSizes =
+  //       gpuLoweringConfig.getStaticTilingLevelSizes(reduction, op);
+  //   size = reductionTileSizes.size();
+  // }
   // if (size > numLoops) {
   //   return op->emitOpError("expected number of reduction tile size is equal
   //   or "
   //                          "less than number of loops");
   // }
-  for (size_t i = 0; i < size; ++i) {
-    if (reductionTileSizes[i] > 0 &&
-        llvm::cast<linalg::LinalgOp>(op).getIteratorTypesArray()[i] !=
-            utils::IteratorType::reduction) {
-      return op->emitOpError(
-          "expected to non-zero reduction tile has reduction iterator");
-    }
-  }
-
-  SmallVector<int64_t> workgroupTileSizes =
-      gpuLoweringConfig.getWorkgroupTileSizes();
-  size = workgroupTileSizes.size();
+  // for (size_t i = 0; i < size; ++i) {
+  // if (reductionTileSizes[i] > 0 &&
+  //     llvm::cast<linalg::LinalgOp>(op).getIteratorTypesArray()[i] !=
+  //         utils::IteratorType::reduction) {
+  //   return op->emitOpError(
+  //       "expected to non-zero reduction tile has reduction iterator");
+  // }
+  // }
 
-  for (size_t i = 0; i < size; ++i) {
-    if (workgroupTileSizes[i] > 0 &&
-        llvm::cast<linalg::LinalgOp>(op).getIteratorTypesArray()[i] !=
-            utils::IteratorType::parallel) {
-      return op->emitOpError(
-          "expected to non-zero workgroup tile has parallel iterator");
-    }
-  }
+  // SmallVector<int64_t> workgroupTileSizes =
+  //     gpuLoweringConfig.getWorkgroupTileSizes();
+  // size = workgroupTileSizes.size();
 
-  if (pipeline == CodeGenPipeline::LLVMGPUTileAndFuse ||
-      pipeline == CodeGenPipeline::LLVMGPUVectorDistribute) {
-    return success();
-  }
+  // for (size_t i = 0; i < size; ++i) {
+  // if (workgroupTileSizes[i] > 0 &&
+  //     llvm::cast<linalg::LinalgOp>(op).getIteratorTypesArray()[i] !=
+  //         utils::IteratorType::parallel) {
+  //   return op->emitOpError(
+  //       "expected to non-zero workgroup tile has parallel iterator");
+  // }
+  // }
 
-  // Only verify batched and unbatched matmul.
-  if (!isa<linalg::MatmulOp, linalg::BatchMatmulOp>(op)) {
+  if (pipeline == CodeGenPipeline::LLVMGPUVectorDistribute) {
     return success();
   }