v2025.03.02

The release updates XED according to Intel's latest ISA publications, including AVX10.2 (Revision 3.0) and APX (Revision 6.0) architecture specifications.
This release also introduces major enhancements to the decoder control APIs.

ISA Updates

• Added new APX instructions that promote the Diamond Rapids ISA.
• Added support for AVX10.2 mnemonic renames.
• Improved definitions for Intel SDM-recommended multi-byte NOPs (See #340).
• Fixed ISA-SET discrepancy for FISTTP.
• Corrected element types for VCVTQQ2PD and VGET{MANT,EXP}PBF16 instructions.
• Refined TSX ISA definition for accurate disassembly representation.
• Dropped compatibility mode SYSCALL per Intel's latest FRED specification.
• Added missing PROTECTED_MODE and NOP XED attributes for existing ISA.

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General

• Python APIs: The _py binding APIs are now autogenerated during the build for an accurate representation of the chosen build kit.
  For more information, check the xed\pyext\examples\README.md file.
• Python APIs example: Enhancements for the CFFI example and provided XedPy class.
• Updated the XED build to support Clang versions 17 and 18.
• Improved XED examples documentation and source-code comments.
• Simplified the encode request for AVX10/256VL Embedded Rounding Control instructions by setting only the ROUNDC XED operand.

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Fixes

• Fixed UBSan errors (closes #339).
• Fixed Sierra-Forest and other chip-excluded builds using the --no-{chip} build knobs (fixes #343).
• Corrected SIB segment mapping for the R21 register (fixes #340).
• Internal improvements and code cleanup (fixes #340).

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Decoder

• Added REAL-mode legality checks (INVALID_MODE error for illegal instructions).
• Disassembler: Added support for Intel's recommended APX assembly syntax for NF (No Flags) and DFV (Default Flags Values) instructions.
• Enhanced APIs for APX/DFV instructions to ensure simplicity and efficiency. See the API reference page and the xed-ex1.c example for more details.

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API Improvements for Decoder ISA Control

The XED decoder control APIs now fully support the xed_chip_features_t structure, offering greater flexibility and control compared to the
xed_chip_enum_t concept, enabling users to customize feature sets with precision.

• Improved the xed_chip_features_t APIs to provide fine-grained control over ISA initialization.
  This approach is now recommended over the raw xed3_operand_set_* APIs.
• Introduced a new API, xed_set_decoder_modes(), which allows explicit initialization of decoder modes with improved performance through one-time decoder ISA initialization.

Backward Compatibility

• Backward compatibility for existing APIs is maintained.
• Backward compatibility for decoder initialization of several ISA features has been deprecated.
  Previously default-on features like P4 (PAUSE), LZCNT (replacing BSR), and TZCNT (replacing BSF) are now disabled by default unless explicitly enabled by users through the raw XED setter APIs or the chip/chip-features APIs.

Decoder PREFETCH as NOP - New Capability

• Based on decoder ISA initialization, the XED decoder now returns NOPs instead of PREFETCH instructions when PREFETCH is not supported by the chip/features. Previously, PREFETCH instructions were returned as illegal if they were unsupported by the XED chip.

Usage Example

• For detailed usage guidance, refer to the XED xed-ex4.c example tool, which includes decoder initialization recommendations for dual-encoding ISA.

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Full Changelog: v2024.11.04...v2025.03.02

v2024.11.04

The release updates XED according to Intel's latest ISA publications, as detailed in ISE054, ISE055 and AVX10.2-rev2.0.

This version includes support for:

• Intel Diamond Rapids (DMR) chip
• Diamond Rapids AMX instructions
• MOVRS and AVX10-MOVRS instructions
• SM4 EVEX instructions
• MSR-IMM instructions (including APX-promoted variants)
• Encoding updates for various AVX10.2 instructions
• Other updates across XED chip definitions

General

• Shared Library Build for Python: Introduces a unique XED shared library build, exposing all XED APIs via a shared library object.
  This enables the library to be loaded in Python environments, allowing interaction with XED using Python APIs.
  See the examples in pyext/README.md for more details. (Closes #302)
• Disassembler Enhancements: Adds support for emitting CS/DS ignored branch hint prefixes, configurable through the xed_format_options_t structure.
• Updates minimum Python requirement from 3.8 to 3.9.
• Improves Internal ISA definition APX files (See #338)

Fixes

• Resolves C11 build warnings with GCC (Fixes #332, Closes #333)
• Improves length and error reporting for illegal instructions caused by a zeroed EVEX map (Resolves #334)

Full Changelog: v2024.09.09...v2024.11.04

v2024.09.09

General:

• Set the default security build level to 2, enabling the build of a more secure C library by default. If needed, users can lower the security level using the --security-level=1 build option.

Add:

• Add AVX10/256 VL-ignored (Neither SAE nor Embedded-RC behavior) instructions.
• Add ENC2 support for AVX10/256VL Embedded-RC instructions.

Fix:

• Fix potential buffer overflow in ILD (resolves #331)
• Resolve Python 3.12 Regex syntax warnings.

Full Changelog: v2024.08.15...v2024.09.09

v2024.08.15

The release adds support for Intel Advanced Vector Extensions 10.2 (Intel® AVX10.2) ISA, compliant with the AVX10.2 architecture specification rev-1.0 (July 2024).

Added:

• Decoder and encoder support for Intel AVX10.2 new ISA (No ENC2 support for YMM embedded-RC)

Fixed:

• MPX: Removed wrong support for 16-bit addressing variants (#57)

Full Changelog: v2024.05.20...v2024.08.15

v2024.05.20

General:

• Remove a deprecated pin-crt build option

Added:

• Support APX zero-upper recommended assembly syntax for IMUL and SETcc instructions
• Update the xed_operand_values_mandatory_66_prefix() API to support scalable
  instructions introduced with APX
• Enhance ENC2 support for legacy instructions with a mandatory 0xF2/0xF3 prefix
• Integrate an encoding bits emitter for the xed-ex1.c example tool (available in verbose mode)

Fixed:

• Add Missing MSR operand for U{WR,RD}MSR and WRMSRNS instructions
• Fix build errors when the no-amd option is enabled and the object area is not clean

Python Code Quality Improvements:

• Simplify the process of adding mbuild to PYTHONPATH (resolves #323)
• Remove duplicate print utilities in read_xed_db.py (resolves #325)
• Create enums for type and emit_type in actions.py (resolves #326)

We sincerely thank all members of the XED community for their essential contributions.

Full Changelog: v2024.04.01...v2024.05.20

v2024.04.01

This release updates XED according to Intel's latest APX spec (Rev-04), April 2024.

It includes:

• Remove promoted SHA and KeyLocker EVEX instructions
• Encoding update for URDMSR/UWRMSR
• Addition of missing CPUID sensitivity for promoted POPCNT EVEX instruction
• Update the handling of EVEX.U and reinterpretation to X4

General:

• Enable a secured build using a new --security-level mfile.py knob (1->Medium, 2->High, 3->Highest).
  The default level is 1 (will be raised to 2 in a future release)
  Please expect performance degradation with level 3.
• Drop the ICC/ICL build options using mfile.py

Added:

• AMX: Support the restriction of illegal register combination (Solves #303)
• Disassembler: Print sequential registers using "+(N-1)" notation
• Add ENC2 support for Intel APX architecture (TBD: REX2 for EGPR support)
• Add ENC2 support for KOP instructions

Fixed:

• ISA definition fixes (APX/MOVDIR64B missing operands, Fix CPUID for SYS{ENTER,EXIT}, fix MMX extensions)
• RFLAGS: Fix width definition and wrong duplicated operands for several instructions (Solves #320)
• Fix CPL definition for ENQCMDS (Solves #311)
• Fix CPL definition for LGDT (Solves #312)
• Fix CPL definition for VMCALL (Solves #313)
• Several bug fixes and improvements for the ENC2 library.
  For a list of unsupported IFORMS, please check the enc2_unsupported_ref.json file.
• Fix build with the clang built of llvm-project trunk (Solves #315)

Modified:

• Improve Python code quality (Solves #314, Solves #317)

We express our gratitude to all members of the XED community for their valuable contributions.

Full Changelog: v2023.12.19...v2024.04.01

v2023.12.19

This release updates XED according to Intel APX (Rev-03) and Intel AVX10 (Rev-02) architecture specifications, December 2023.

General:

• The XED user guide was updated with explanations for APX, AVX10, and more (https://intelxed.github.io/)
• Updated Python version requirement and documentation to 3.8 (closes #306)

Added:

• Added new APX promoted instructions: RAO-INT and USER-MSR (APX Arch Spec Rev-03)
• Added a complete XED encoder support for Intel APX architecture
• APX(CCMPcc/CTESTcc): Added operand parser API that extracts the default-flags-values from XED DFV pseudo-register
• Updated APX CPUID sensitivity with additional Legacy/VEX CPUID records
• FRED: Added compatibility mode SYSCALL

Fixed:

• Fixed missing REX2 prefix restriction for several legacy instructions
• APX/JMPABS: Added missing RIP suppressed operand
• ENC2: Fixed the encoding of instruction's operands
• Fixed CPUID records for KEYLOCKER and MOVDIR instructions

Modified:

• Updated AVX10 CPUID sensitivity of 64-bit KMASK instructions (AVX10 Arch Spec Rev-02)
• Improved Python code for genutil.py (resolves #307)

Full Changelog: v2023.10.11...v2023.12.19

v2023.10.11

This release updates CPUs and instructions according to ISE (Intel® Architecture Instruction Set Extensions and Future Features) rev-050, September 2023.

Added:

• New USER_MSR and FRED instructions
• New chips: Emerald Rapids, Clearwater Forest and Panther Lake
• ENC2 updates with support for AMX/EVEX, IMM dest operand and EVEX
  scalable operand size instructions
• Instructions for contributing to the Intel® XED project (README.md)

Fixed:

• xed_agen() API: Avoid potential signed integer overflow (closes #305)
• AMX: Fixed element types and updated extension definition

Modified:

• Updated DAZ behavior of several AVX_NE_CONVERT instructions
• Dropped Grand Ridge (No new ISA over SRF)
• Updated PBNDKB CPUID name

Full Changelog: v2023.08.21...v2023.10.11

v2023.08.21

The release adds support for Intel Advanced Vector Extensions 10 (Intel® AVX10), and Intel® APX.

Full Changelog: v2023.07.09...v2023.08.21

v2023.07.09

The release adds support for new CPUs and instructions according to ISE (Intel Architecture Instruction Set Extensions and Future Features) rev-049, June 2023.

Added:

• Added new chips: Arrow-Lake and Lunar-Lake
• Added new instructions: AVX-VNNI-INT16, SHA512, SM3, SM4 and PBNDKB
• Updated SRF with UINTR and ENQCMD support

Full Changelog: v2023.06.07...v2023.07.09